FPGA Design Flow

1
FPGA Design Flow
Verilog RTL Coding
Tools
Design Stage
Text Editor Emacs, Nedit, Vi
Verilog Design
Functional/Gate simulation Verification
Modelsim SE Leda
Verification
sdc
Xilinx ISE - XST Synplify Pro
Synthesis
Logic Synthesis
Xilinx ISE Xilinx Impact
Pyhsical Design Implementation
ucf
Physical Layout
Device Configuration
2
Digital Design Flow
Verilog Coding
Tools
Design Stage
Text Editor Emacs, Nedit, Vi
Verilog Design
Functional/Gate Simulation/Verification
Mentor - Modelsim SE Synopsys - Leda
Verification
Synposys - Design Compiler
Synthesis
Logic Synthesis
scr
Synopsys - TetraMax Mentor - Fastscan
Test Insertion
Test-Insertion
test.scr
Synopsys - Primetime
Static Timing Anal.
Cadence - Sensemble/ SOC Encounter Synopsys -
Apolllo
Place Route
Static Timing Analysis
_pre.sdf
techfile.lef techfile.gcf .lef .tlf .def
Floorplanning/ Place Route
Cadence - CTgen
Clock Tree Insertion
Synopsys - StarRXT Cadence - Pearl
Timing Extraction
Clock Tree Insertion Final Layout
ctgen.con
Cadence - Assura, Dracula Mentor Callibre
DRC/ANT Checking
_post.sdf
Timing Extraction
Cadence - Assura, Dracula Mentor Callibre
LVS
Final Design Check DRC/LVS
gds2
3
Analogue Design Flow
Schematic Entry
Tools
Design Stage
Composer
Schematic Entry
Simulation
Spectre
Simulation
Virtuosso
Layout
Assura Calibre
Pyhsical Verification/ Extraction
Layout
techfile.lef techfile.gcf .lef .tlf .def
Spectre
Post-Layout Simulation
Physical Verification / Extraction
Post-Layout Simulation
gds2
4
Mixed Signal Design Flow
Cadence - SpectreVerilog Cadence -UltraSim
Analog Flow
Digital Flow
Co-simulation Environement
Verilog Coding
Behavioural Modelling
Schematic Entry
Functional/Gate Simulation/Verification
Simulation
Logic Synthesis
scr
Test-Insertion
test.scr
techfile.lef techfile.gcf .lef .tlf .def
Layout
Static Timing Analysis
_pre.sdf
techfile.lef techfile.gcf .lef .tlf .def
Floorplanning/ Place Route
Physical Verification / Extraction
Clock Tree Insertion Final Layout
ctgen.con
_pst.sdf
Timing Extraction
Post-Layout Simulation
gds2
Final Design Check DRC/LVS
gds2