D FlipFlop

1
D Flip-Flop

• Digital Logic ELET 1133
• Kleitz

2
Logic Diagram
D
G
3
Gated D Flip-Flop 7475

• Data (or Delay) flip flop
• clocked so that the output Q will follow the
  input when the clock is high.
• The gate is transparent.
• Q remains latched when clock is low.
• Read data out when clock is low.
• Write data in when clock is high.

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7475 Pin Diagram
4 D flip-flops on one integrated circuit.
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7475 D Flip Flop Timing Example
G D D Q
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7475 D Flip Flop Timing Example
G D D Q
Gate is high and D high so reset initially. Then
D sets high. No change when clock is low.
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7475 D Flip Flop Timing Example
G D D Q
Reset, then set during clock pulse. No change
when clock is low.
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D Flip Flop Application

• Use for comparisons
• is the data higher or lower than it was one
  clock cycle ago.
• Use to hold data until ready to process it.

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D Flip Flop Idea
Holds all data to start at the same time.
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Clock Waveform

• Clock can have narrow pulse at set frequency.
• Name narrow pulse over spike.

Make pulse narrow so that D does not change
within the pulse.
11
Making a Narrow Pulse
12
Narrow Pulse Generation
A
B
AB
13
Edge Triggered

• changes only occur on...

rising or positive edge
Falling or negative edge
Cp
Cp
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7474 D Flip Flop

• Positive Edge Triggered
• Output will only change on the rising edge of a
  clock pulse.
• not during pulse
• Asynchronous Inputs
• asynchronous set
• asynchronous reset

15
Clock

• Synchronous
• with
• clock
• Asynchronous
• not
• with
• clock

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7474 D flip flop

• 2 flip flops in one package
• Altera drawing
• 7474
• generic D

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Asynchronous Inputs

• Asynchronous set
• active low
• low logic on this input will immediately set Q
  1.
• connect to Vcc if not used.
• Asynchronous reset
• active low
• low logic on this input will immediately set Q
  0.
• connect to Vcc if not used.

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7474 D Flip Flop Timing Example (Asynchronous
Inputs Held High)
G D D Q
hold
set
reset
reset
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7475 D Flip Flop Timing Example Problem 10-10
G D Q
Q follows D when enable is on. Otherwise Q
remains where it was.
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7474 D Flip Flop Timing Example Problem 10-16
Q D at positive gate edge.
G SD RD D Q
AS
AR
AR
SR
SS
SS