Control Multicycle Implementation

1
Control Multicycle Implementation
2
Datapath from last lecture
3
Instruction Fetch

• Fetch instruction from memory and increment PC
• Can be performed at same time as no contention
  for resources
• Register transfers
• IR MemoryPC
• PC PC 4

4
Instruction Decode and reg fetch

• Do not know what instruction is until the end of
  this step
• gt can only perform actions
• Applicable to all instructions
• That are not harmful
• Most instructions require values from register
  file
• Also ALU not being used so can calculate a branch
  target

5
Instruction Decode and reg fetch

• Register transfers
• A RegIR25-21
• B RegIR20 16
• ALUOut PC (sign-extend(IR15-0) ltlt 2)

6
Step 3

• Action taken is dependent on Instruction class
• Execution or R-type instructions
• ALUOut A op B
• Memory address computation for lw and sw
• ALUOut A sign-extend(IR15-0)
• Branch completion for Branch instructions
• If (A B) PC ALUOut
• Jump
• PC PC31-28 (IR25 0 ltlt 2)

7
Step 4

• Again action taken is dependent on instruction
• Memory reference (lw)
• MDR memoryALUOut
• Memory reference (sw)
• MemoryALUOut B
• R-Type
• RegIR15 11 ALUOut

8
Step 5

• Memory Read completion Step
• Register Transfer
• RegIR20-16 MDR

9
Summary of actions
10
Defining Control

• Control for single cycle implementation a
  combination circuit
• Multicycle control more complex as instruction
  execution broken into steps
• In multicycle implementation need to specify
• Signals set for the step
• The next step
• Two main technques for implementation
• Finite state machines
• Microprograming

11
Finite State Machines
12
Complete Finite State Machine
13
CPI of Multicycle CPU

• What is the CPI of this multicycle implementation
  assuming each state requires 1 clock cycle and
  the following instruction mix
• 22 loads
• 11 stores
• 49 R-Type Instructions
• 16 branches
• 2 Jumps