Control Multicycle Implementation

1
Control Multicycle Implementation
2
Datapath from last lecture
3
Instruction Fetch

• Fetch instruction from memory and increment PC
• Can be performed at same time as no contention
  for resources
• Register transfers
• IR MemoryPC
• PC PC 4

4
Instruction Decode and reg fetch

• Do not know what instruction is until the end of
  this step
• gt can only perform actions
• Applicable to all instructions
• That are not harmful
• Most instructions require values from register
  file
• Also ALU not being used so can calculate a branch
  target

5
Instruction Decode and reg fetch

• Register transfers
• A RegIR25-21
• B RegIR20 16
• ALUOut PC (sign-extend(IR15-0) ltlt 2)

6
Step 3

• Action taken is dependent on Instruction class
• Execution or R-type instructions
• ALUOut A op B
• Memory address computation for lw and sw
• ALUOut A sign-extend(IR15-0)
• Branch completion for Branch instructions
• If (A B) PC ALUOut
• Jump
• PC PC31-28 (IR25 0 ltlt 2)

7
Step 4

• Again action taken is dependent on instruction
• Memory reference (lw)
• MDR memoryALUOut
• Memory reference (sw)
• MemoryALUOut B
• R-Type
• RegIR15 11 ALUOut

8
Step 5

• Memory Read completion Step
• Register Transfer
• RegIR20-16 MDR

9
Summary of actions
10
Defining Control

• Control for single cycle implementation a
  combination circuit
• Multicycle control more complex as instruction
  execution broken into steps
• In multicycle implementation need to specify
• Signals set for the step
• The next step
• Two main technques for implementation
• Finite state machines
• Microprograming

11
Finite State Machines
12
Complete Finite State Machine
13
CPI of Multicycle CPU

• What is the CPI of this multicycle implementation
  assuming each state requires 1 clock cycle and
  the following instruction mix
• 22 loads
• 11 stores
• 49 R-Type Instructions
• 16 branches
• 2 Jumps

14
Microprogramming

• What are the microinstructions ?

15
Microprogramming

• A specification methodology
• appropriate if hundreds of opcodes, modes,
  cycles, etc.
• signals specified symbolically using
  microinstructions
• Will two implementations of the same architecture
  have the same microcode?
• What would a microassembler do?

16
Microinstruction format
17
Maximally vs. Minimally Encoded

• No encoding
• 1 bit for each datapath operation
• faster, requires more memory (logic)
• used for Vax 780 an astonishing 400K of memory!
• Lots of encoding
• send the microinstructions through logic to get
  control signals
• uses less memory, slower
• Historical context of CISC
• Too much logic to put on a single chip with
  everything else
• Use a ROM (or even RAM) to hold the microcode
• Its easy to add new instructions

18
Microcode Trade-offs

• Distinction between specification and
  implementation is sometimes blurred
• Specification Advantages
• Easy to design and write
• Design architecture and microcode in parallel
• Implementation (off-chip ROM) Advantages
• Easy to change since values are in memory
• Can emulate other architectures
• Can make use of internal registers
• Implementation Disadvantages, SLOWER now that
• Control is implemented on same chip as processor
• ROM is no longer faster than RAM
• No need to go back and make changes