8'3'3 8'3'3Optimizing the number of stages during the design of HighSpeed CMOS Logic Networks To dec

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8.3.3       
8.3.3 Optimizing the number of stages during
the design of High-Speed CMOS Logic Networks To
decrease the total delay time in the logic chain,
inverters are often introduced in between the
stages. This is because of the fact that, logical
effort of an inverter is ginv 1 and as the
product of gs in the logical chain remains
unaffected, as G g1g2gN remains same.
Numerical value of the path effort, F GH also
does not change. Delay time minimization is
Total path Delay is As D decreases with
increasing N, the inclusion of inverters is a
useful technique.
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A minimum delay through the cascade is achieved
if for every i This is consistent
with our conclusions for the simple 2-stage
inverter chain. The optimum path effort is thus
so that the fastest design is where each stage
has This is the main equation of logical
effort. The comparison of an N-stage logic chain
allows us to find the value of F. Each staged
can be sized to accommodate the optimum
electrical effort value , The optimized path
delay is then where . It is the sum of the
parasitic delays.  
In general, Pref for an inverter is the smallest,
with multiple-input gates exhibiting larger
parasitic delay times. One simple estimate is to
write It is the parasitic delay for an n-input
gate.
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8.3.3        8.3.4 Logical areaLogical
area of a CMOS logic gate is defined by Where L
is the channel length and W is determined by
sizing.The logical area of 1x inverter (NOT) is
The logical area of scaled inverter (NOT) is
The logical area of NAND2 gate is The
logical area of NOR2 gate is For a network with
logical M gates , the logical area is It is
important to note that, the above areas does not
include the areas occupied by drain, source,
well, interconnect wiring etc.
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       8.3.5 BranchingWhen the logic gate
drives two or more gates, the data path splits.
The capacitance contributed by the off path
should also be considered in to account.
  (Node)2 (Node)1
Fig.26 Illustration of the effect of
branching on the total delayThe effect of
branching is taken in to consideration by
introducing the branching effort at b at every
branching point.
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Branching effort, b is given by , where Cpath
is the capacitance in the mainlogic path and CT
Cpath Coff, . Where Coff is the capacitance
that are of the branching path.b gt 1 and
accounts for the additional loading. The path
branching effort is, where bi are the
individual branching efforts. The branching
effort at node1 of Fig.26is The branching
effort at node2 of Fig.26is The path
branching effort for the selected path indicated
by arrows is then, problem 8.9
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Advanced Techniques in CMOS Logic
Circuits(Chapter 9 of John P.Uyemura)
9.1 Mirror Circuits
Fig.34 Circuit of XOR gate Fig.35
General Structure of a pseudo-nMOS gate
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In the truth table of XOR gate, there are equal
number of input combinations that produce 0s
and 1s. Output 0s imply that an nFET chain is
conducting to ground, while an output 1 means
that a pFET group provides support from the power
supply. A mirror circuit uses the same FET
topology for the nFET and pFETs. Applying this to
the XOR function yields the circuit in fig.34.
The input combinations are shown for each branch.
The mirror effect can be understood by placing
a mirror along the output line, facing either up
or down. The mirror image seen in the mirror will
be the other side of the circuit. The advantage
of the mirror circuit are more symmetric layouts
and shorter rise and fall times.

• 9.1 Mirror Circuits

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9.2 Pseudo-nMOS
Adding a single pFET to otherwise nFET-only
circuit produces a logic family called
Pseudo-nMOS. It uses fewer FETs because only the
nFET logic block is needed to create the logic.
For N inputs, a pseudo-nMOS logic gate requires
(N 1) FETs. In conventional CMOS, the pFET
group is added to reduce the DC power
dissipation, but the logic is superfluous.
Standard N-input CMOS gates use 2N FETs. The
basic topology of a pseudo-nMOS gate is shown in
Fig.35. The single pFET is biased active since
the grounded gate gives VSGp VDD. It acts as a
pull-up that tries to pull the output f to the
power supply voltage VDD. If the switch is open ,
the pFET pulls up the output to a voltage VOH
VDD. If the nFET switch is closed, then the array
acts as a pull-down device that tries to pull f
down to ground. The disadvantage is that, as pFET
is always biased ON, VOL can never achieve the
ideal value of 0V. This can be overcome by
adjusting the size of pFET. The calculation of
the size of pFET is done as follows Consider a
simple inverter. If the input is VDD, output is
VOL. If VOL is assumed to be small, then the pFET
will be saturated while the nFET operates in the
non-saturation region. The KCL equation thus
assumes the form  
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Which is a quadratic equation for VOL. Solving,
we get, Thus the value of VOL depends on the
ratio . With the increase inthe
device ratio, VOL will decrease. General
pseudo-nMOS logic gates are designed using the
same nFET arrays as in standard CMOS. NOR2 and
NAND2 are shown in fig.36 and 37 respectively.
The NOR2 gate is based on the same ?-values since
the worst-case pull-down situation is when only a
single nFET is active. The same argument holds
for n-input NOR gate. The NAND2 gate in Fig.37
(b) is complicated by the series nFETs. To
obtain the same pull-down characteristics of the
inverter, the logic FETs must be increased to 2?n
to provide the same total nFET resistance from
the output to ground. This is a general problem
with pseudo-nMOS gates that require series logic
FETs. A basic AOI circuit is shown in Fig.37 (c)
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Fig. 37 (a) Pseudo-nMOS NAND2 gate Fig.37
(b) Pseudo-nMOS NOR2 gate Fig.37 (c)
Pseudo-nMOS AOI gate


Boolean Expressions
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9.3     Tri-state CircuitsA tri-state circuit
produces the usual 0 and 1 voltages, but also has
a third high-impedance Z (or Hi-Z) state that is
the same as an open circuit. Tri-state circuits
are useful for isolating circuits from common bus
lines. The symbol for a tri-state inverter is
shown in fig.38 (a). Fig.38 (a)
Symbol of Tri-state inverter Fig.38 (b) CMOS
circuit of Tri-state inverter 
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9.4 Clocked CMOS(C2MOS)   In C2MOS circuits
a clock signal is applied to have control over
the operation of the entire CMOS circuit. The
clock signal ? (or clk) is a periodic waveform
with a well defined period T (sec) and
frequency f (Hz) such that
Fig 39 wave form of clock ? (t) and its
complement
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During this interval, the FET logic arrays are
not connected to the output, so the inputs have
no effect. Instead, the output voltage is held on
Cout until the clock returns to a value ? 1.
Fig.40 Structure of C2MOS gate Fig.41 Circuit of
NAND2 gate Fig.42 Circuit of NOR2 gate  
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If ? (t) is defined to have a minimum value of 0
V and a maximum of VDD, then so that the
clocks overlap slightly during a transition. It
may be advantageous to create a set of clocks
that are truly non-overlapping for all times.

• The general structure of a C2MOS gate is shown in
  fig.40. It is composed of a static logic circuit
• with tri-state output network made up of FETs M1
  and M2 that is controlled by ? and . When
• 1, both M1 and M2 are active. Since both the
  pFET and nFET logic blocks are connected to
• the output node, the circuit degenerates to a
  standard static logic gate. The output f(a,b,c)
  is
• valid during this time, establishing the voltage
  Vout on the output capacitance Cout. When the
• clock changes to a value ? 0, both M1 and M2
  are in cutoff, so that the output is in high-
• impedance state Hi-Z.

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The transistor arrays are designed using the same
technique as for standard logic gates. The
circuits of a NAND2 and NOR2 are shown fig.41
and fig.42 respectively. The presence of the
series-connected clocking FETs automatically
lengthens both the rise and fall times of the
circuit.Advantages 1)      The Clock
controls the entire operation of the logic
gate.2)      New group of data bits enter the
network during every clock cycle.
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Disadvantages of Clocked CMOS(C2MOS)
Circuit
1)      Output node cannot hold the charge on
Vout for a very long time due to phenomenon
called charge leakage. 2)      Lower limit on
the clock frequency will be laid by the
phenomenon of charge leakage. This makes the
operation of the logic to be done at lower
frequency range only.