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Circuit Characterisation

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52.430 VLSI' Circuit Characterisation. 1 ... It is observed that Cd Cg/5 ... Contact Replication. single conductor may not be able to supply all circuits ... – PowerPoint PPT presentation

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Title: Circuit Characterisation


1
Circuit Characterisation
2
MOS Structure
  • MOS structures consist of
  • diffusion layers
  • polysilicon layers
  • metal layers
  • separated by
  • insulating layers
  • Each layer has resistance and capacitance (which
    are fundamental to performance estimation)
  • plus some inductance
  • We need models to estimate the resulting
    performance in terms of signal delays and power
    dissipation

3
Resistance Estimation
  • Where
  • ? is resistivity t is thickness
  • RS is sheet resistance in ohms/square

4
Channel resistance of a MOS transistor - 1
  • Where µ is the surface mobility of the majority
    carriers
  • Examples
  • Metal_1 metal_2 0.07 O/square
  • Polysilicon 20.00 O/square

5
Channel resistance of a MOS transistor - 2
  • For non-rectangular regions, decompose into
    simple regions of known resistances
  • For contacts and vias the resistance is dependent
    upon
  • The materials involved
  • The area of contact

6
Capacitance Estimation - 1
  • Switching speed is dependent upon
  • Parasitic capacitances
  • Interconnection capacitances
  • Transistor and conductor resistances
  • The load capacitance of a CMOS device is the sum
    of
  • Gate capacitance
  • Diffusion capacitance
  • Routing capacitance

7
Capacitance Estimation - 2
  • System performance is part of the design
    specification
  • So knowledge of capacitances is essential
  • These are
  • Cgs, Cgd gate-to-channel capacitances at
    source and drain regions
  • Cgb gate-to-bulk (substrate)
  • Csb source-to-bulk
  • Cdb drain-to-bulk

8
Gate Capacitance
  • Cg Cgb Cgs Cgd
  • Gate capacitance varies according to whether the
    device is OFF, in the LINEAR region, or in the
    SATURATED region
  • For calculation of delays, use
  • Cg CoxideA
  • A is the gate area
  • and
  • Coxide e0er(oxide)/toxide 10-3 pF/µm2

9
Diffusion Capacitance
  • The source and drain regions are shallow
    diffusions
  • Diffusions also act as wires
  • Assuming zero DC bias across the junction
  • Cd Cjab Cp(2a2b)
  • Where
  • Cj is the junction capacitance per µm2
    10-4pF/ µm2
  • Cp is the periphery capacitance per µm
    10-4pF/ µm
  • a and b are the width and length of the
    diffusion region (µm)
  • For non-zero DC bias both Cj and Cp are functions
    of voltage (due to resulting changes in the
    depletion layer thickness)

10
SPICE Modelling of MOS Capacitances
  • In detailed modelling the following need to be
    taken into account
  • Dimensions
  • Oxide layer thickness
  • Fringing fields correction factors
  • Junction potential
  • Zero-bias capacitance/area
  • Zero-bias capacitance/periphery
  • Appropriate grading coefficients

11
  • It is observed that Cd Cg/5
  • i.e. gate capacitance dominates the loading in
    current CMOS technologies
  • Oxides are thinner and diffusions shallower than
    a decade ago

12
Routing Capacitance - 1
  • Single wire
  • Take the sum of
  • The parallel plate model
  • with
  • Fringing field corrections
  • (which effectively increase the plate area)

13
Routing Capacitance - 2
  • Multiple conductors
  • There are complex inter-layer capacitance
    interactions
  • Empirical formulae have been developed
  • Accurate 3-D calculations are not feasible
  • Dielectric thickness varies
  • There is tolerance on etching
  • Use worst-case values
  • i.e. assume
  • maximum width and thinnest dielectric for delay
    and power calculations
  • Minimum width and maximum thickness for race
    conditions

14
Distributed RC Effects - 1
  • For long wires with appreciable sheet resistance,
    propagation delays can be significant
  • Take
  • where
  • r is resistance per unit length
  • C is capacitance per unit length
  • l is the length of the wire

15
Distributed RC Effects - 2
  • Hence a long polysilicon wire is a bad idea
  • e.g. if r 20 O/µm C 410-4 pF/µm l
    2mm
  • Then
  • Divide the wire into two sections connected by a
    buffer
  • Thus significant improvement can be obtained by
    segmenting the bus.
  • Use of wider wire would reduce resistance at the
    expense of increasing capacitance

16
Distributed RC Effects Example 1
  • Consider a 50pF clock load over a 10mm chip in
    1µm metal
  • Assume that the 50pF is distributed along the
    line
  • Assume that the clock buffer is in the
    corner
  • Take r 510-2 O/µm

r/2
50pF/20mm
length2
17
Distributed RC Effects Example 2
  • Now widen the clock line to, say, 20µm
  • and distribute it from the chip centre
  • length/width goes down from (20103/1) to
    (10103/20)
  • a factor of 40
  • so
  • i.e. 2 orders of magnitude reduction in
    propagation delay
  • Clock distribution is vital in high-speed, high
    density chips
  • Balance capacitance increase against resistance
    decrease

18
Representative Capacitance Values (1µ process)
  • Cg 2 fF
  • (for n) Cj .3 fF (for p) Cj .5 fF
  • (for n) Cp .4 fF (for p) Cp .4 fF

19
Wire-length Design Guide - 1
  • Signal (wire) delay should be ltlt gate delay tw
    ltlt tg
  • But, as we have seen, tw (r.c.l2/2)
  • Therefore the condition becomes
  • Note that this applies for lightly loaded
    interconnects

20
Wire-length Design Guide - 2
  • Ignoring RC wire delays
  • And assuming gate delays of 100 500 ps

21
Inductance, L
  • Inductance is mainly a problem with bond-wire in
    large, high-speed I/O buffers
  • dV L.dI/dt (voltage change)
  • Package inductance is quoted by maufacturers as
    10 nH
  • For on-chip wires the value is 2x10-2 nH/mm
  • As processes shrink on-chip inductances may
    increase in significance
  • For a conductor on a chip
  • where µ is magnetic permeability
  • (1.257 x 10-6 Hm-1)
  • h is height above substrate
  • W is the width of the conductor

22
Switching Characteristics
  • Speed is limited by the time to charge/discharge
    a load capacitance
  • tr time for rise from 10 to 90 of steady
    state value
  • tf time for fall from 90 to 10 of steady
    state value
  • td time difference between input transition and
    50 output level
  • tdhigh-to-low is not necessarily equal to
    tdlow-to-high
  • Both analytic and empirical models can be
    developed to understand the parameters affecting
    delays

23
Analytic Models - 1
  • Fall time calculation
  • initially the n-device is off
  • CL is charged to VDD
  • Apply Vgs VDD at Vin
  • Fall time tf consists of
  • tf1 Vout drops from .9VDD to (VDD-Vtn)
  • tf2 Vout drops from (VDD-Vtn) to 0.1 VDD
  • k 3 to 4
  • VDD 3 to 5 V
  • Vtn .5 to 1 V
  • So, for high-speed circuits
  • minimise CL
  • increase (W/L)
  • increase the supply voltage

24
Analytic Models - 2
  • Rise time calculation
  • as for fall time
  • If the n and p transistors are equally-sized
  • ßn (2 to 3)ßp
  • i.e. tf tr/(2 to 3)
  • For equal fall and rise times, make ßn ßp
  • i.e. Wp (2 to 3)Wn

25
Analytic Models - 3
  • Delay time of a gate
  • Alternatively
  • Where Ap and An .28 are process constants,
    functions of VDD

26
Empirical Models
  • A circuit simulator is used to model the gate in
    question
  • The measured values are then back-substituted
    into delay equations

27
Gate Delays 1
  • These may be approximated by constructing an
    'equivalent' inverter
  • i.e. with pull-down n-transistors and pull-up
    p-transistors which reflect the effective
    strengths of pull-down/pull-up paths
  • e.g. in the diagram
  • Wn Wp for all transistors

28
Gate Delays 2
  • for pull-up (only 1 transistor has to be ON)
  • for pull-down (all transistors must be ON)
  • When ßn1 ßn2 ßn3 ßn
  • For ßp 0.3ßn i.e. tr tf

29
Summary
  • Given
  • m n-transistors k p-transistors
  • In series
  • Tf mtf Tr ktr
  • In parallel
  • Tf tf/m Tr tr/k
  • In the parallel situation, it is assumed that all
    transistors are turned on simultaneously
  • Deviations from ideal conditions include
  • slope of input waveform
  • input capacitance of gate terminal varies with
    applied voltage
  • Vt changes with change of voltage difference
    between the source and substrate

30
Switch-level Models - 1
  • Various transistor-level models exist
  • (i) RC delay model
  • calculate total resistance of pull-up or
    pull-down path
  • capacitances of all nodes lumped onto gate output
  • effective resistance associated with each
    transistor type, size and state

31
Switch-level Models - 2
  • (ii) Penfield-Rubenstein model was developed to
    calculate delays in generalized RC trees
  • e.g.
  • for transistors in series

32
Switch-level Models - 3
  • (iii) Penfield-Rubenstein slope model
  • as (ii) but with recognition of a non-step
    function input waveform
  • Either
  • use transistor-level modeling
  • or simulate gates with SPICE and measure delays
    for test circuits
  • Precise process calibration requires
  • (a) accurate modeling of transistors
  • (b) accurate modeling of parasitic capacitances
  • Achieve (a) via test structures on a chip
  • Achieve (b) by measuring delay and
    reverse-engineer capacitance by comparing delay
    with simulator output

33
Transistor Sizing
  • So far it is assumed that Wp 2 3 x Wn for
    similar rise and fall times
  • Adopting this causes layout area and dynamic
    power dissipation penalties
  • For .5 lt ßn/ßp lt 2
  • Vinv varies by 15
  • So can use equal-sized devices reducing power
    dissipation, increasing circuit density for
    lightly-loaded circuits
  • For significant load, size the n and p
    transistors to yield equal rise and fall times

34
Power Dissipation - 1
  • (i) Static dissipation
  • no DC current path from VDD to VSS, so
    steady-state current (and power) is zero
  • parasitic diodes are reverse-biased and therefore
    provide leakage current
  • at 300K i0 is estimated as .1 .5 nA per device
  • e.g. for inverter at 5 volts, static power
    dissipation 1 nWatt

35
Power Dissipation - 2
  • (ii) dynamic dissipation
  • There will be a transient current pulse
    (short-circuit) while switching from VDD to VSS
  • Psc Imean x VDD
  • Assuming tr tf ( t)
  • where ß ßn ßp
  • ?p period of input waveform
  • Slow rise times can result in significant
    short-circuit dissipation
  • but still less significant than dissipation due
    to charging/discharging of the capacitive load

36
Power Dissipation - 3
  • Dynamic power dissipation is of relevance to I/O
    buffer design when the effect of capacitance is
    included
  • Assuming tr, tf ltlt ?p
  • Note that power dissipation is inversely
    proportional to ?p but independent of device
    parameters
  • Total Dissipation Ps Psc Pd
  • This is used to estimate total power
    consumption

37
Minimising Power
  • (a) DC dissipation
  • reduce to leakage by using complementary logic
  • reduce leakage by using minimum sized devices
  • because leakage varies as the area of diffusion
  • (b) Dynamic dissipation
  • reduce supply voltage (1.5 3 volts)
  • minimise switch capacitance
  • (minimum size devices, consider layout routing
    capacitance)
  • Reduce the effective frequency of the clock
  • (by operating the minimum amount of circuitry at
    high speed)

38
Size of Routing Conductors
Metal power carrying conductors have to be
carefully sized for three reasons
  • Metal Migration
  • This is transport of metal ions and leads to
    deformation of circuitry
  • It is affected by
  • current density
  • temperature
  • crystal structure
  • If current density J gt threshold, dislocation of
    conductor atoms occurs
  • JAl 1 mA/m
  • Power supply integrity
  • Voltage drops can occur due to IR drop during
    charging transients
  • Poor VDD or VSS levels
  • ? poor logic levels
  • ? incorrect gate operations
  • There may also be current spikes if gates change
    close to the clock
  • Requires careful power supply routing
  • RC delay
  • tp rcl2/2
  • so balance r and c contributions

39
Power and Ground Bounce
  • These are part of the power supply integrity
    already mentioned
  • They are fluctuations in voltage when current
    changes rapidly - also known as simultaneous
    switching noise SSN
  • large current spikes with clock transitions
  • clock buffers can have significant ground bounce
    (because of large capacitance)
  • fluctuations up to 1V are tolerable

40
Contact Replication
  • single conductor may not be able to supply all
    circuits
  • This may require a layer change
  • Vias will then be necessary
  • The current density J at the periphery of a via
    should be kept lt .1mA/m
  • Hence use a chain of small windows to maximise
    the periphery

41
Design Margining - 1
  • In general there are three different sources of
    variation in circuit behavior
  • These include
  • temperature
  • supply voltage
  • process variation
  • Circuits must function reliably over all extremes
    of these factors

42
Design Margining - 2
  • (i) Temperature
  • drain current, Ids ? T-3/2
  • commercial specifications require operation in
    range 0ºC ? 79ºC
  • Industrial specifications -40ºC ? 85ºC
  • Military specifications -55ºC ?125ºC
  • Transistors, capacitors and resistors will all
    have temperature variation

43
Design Margining - 3
  • (ii) Supply voltage
  • nominal supplies are 5V, 3.3V or 13V
  • Component tolerances, temperature variation and
    battery condition alter nominal voltages
  • Variation usually 10
  • Some circuits principally analog require
    consideration of voltage coefficient of each
    device

44
Design Margining - 4
  • (iii) Process variation
  • Include variations in
  • width/thickness of oxide/diffusion layers
  • implant doses
  • doping densities

45
Design Margining - 5
  • Strategies
  • Retain components inside 23 standard deviations
    from normal
  • this affects the yield
  • Observe the boundary conditions on transistors
  • fast n- fast p-
  • fast n- slow p-
  • slow n- slow p-
  • slow n- fast p-
  • Simulate circuits for all appropriate boundary
    conditions
  • If the gains of the p- and n- transistors track
    but the threshold voltages do not one might be
    able to combine
  • worst-speed
  • slow n - slow p, highest temperature, lowest
    operating voltage
  • high-speed
  • fast n - fast p, lowest temperature, highest
    operating voltage

46
Yield
  • Model 1
  • where A is chip area
  • D is defect density
  • For large chips and yields lt30
  • Model 2
  • For small chips and yields gt30
  • Yield decreases as area increases
  • To improve yield incorporate redundancy
  • Particularly effective for memory structures

47
Scaling of Transistor Dimensions 1
  • (i) Constant Electric Field
  • Apply a dimensionless factor a to
  • All dimensions (including vertical)
  • Voltages
  • Concentration densities
  • Pstatic and Pd decrease by 1/a2
  • But number of devices per unit area increases by
    a2
  • therefore power density is unchanged

48
Scaling of Transistor Dimensions 2
  • (ii) Constant Voltage
  • VDD is kept constant so the field, E, increases
  • This brings non-linear problems
  • Power density increases by a3
  • (iii) Lateral Scaling
  • Only the gate length is scaled
  • Power density increases by a2

49
Interconnect Layer Scaling
  • Note For a constant chip size many of the
    communication paths do not scale
  • Paths still need to cross the chip

50
Influence of Scaling on MOS-Device
Characteristics - 1
  • See table in DR. McInnes notes
  • Metal lines must carry a higher current with
    respect to cross-sectional area hence metal
    migration
  • As average line length increases capacitance
    increases
  • Power dissipation/gate decreases
  • Hence average gate delay is determined by
    interconnect rather than by gate

51
Influence of Scaling on MOS-Device
Characteristics - 2
  • Over the past decades constant voltage scaling
    has come to dominate
  • Electric field increases, velocity enters
    non-linear region and mobility is no longer
    constant
  • Design problems are
  • Metal migration
  • RC delays in metal wires
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