COMP541%20Combinational%20Logic%20and%20Design

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COMP541Combinational Logic and Design

• Montek Singh
• Jan 25, 2007

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Topics

• What we didnt cover last time
• Other gates, standard forms
• Combinational Design (Ch. 3)
• Real Devices
• Logic Families, Actual ICs, Gate delays
• Propagation delay

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Combinational Logic Design

• Ch. 3 takes us to hierarchical design
• Like youd use for a program of size

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Design Hierarchy

• Just like with large program, to design a large
  chip need hierarchy
• Divide and Conquer
• To create, test, and also to understand
• Block is equivalent to object

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Example

• 9-input odd func (parity for byte)
• Block for schematic is box with labels

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Design Broken Into Modules

• Use 3-input odd functions

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Each Module uses XOR
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Use NAND to Implement XOR

• In case theres no XOR, for example

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Design Hierarchy
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Components in Design

• RHS shows what must be designed

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Reuse is Common

• Certainly forced because of availability of parts
  (chips)
• Also the design cycle was very long
• Now more flexibility with programmable logic
• But still reuse from libraries or intellectual
  property (IP)
• Example buy a PCI design
• Open source, see www.opencores.org
• Note the many logic blocks available in Xilinx
  library

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Flow of CAD System
Replaces Generic Gates with ones available in
Technology Library
Generic Gates

• Netlist is description of connections

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Technology Mapping

• Full custom
• Pixel-Planes chips (machines in lobby)
• Memories, CPUs, etc
• Standard cell
• Library of cells
• Engineer determined interconnection
• Gate arrays
• Small circuits with interconnect

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Hierarchy Example 4-bit Equality

• Example 3-4 in book
• Input 2 vectors A(30) and B(30)
• Output One bit, E, which is 1 if A and B are
  bitwise equal, 0 otherwise

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Design

• Hierarchical design seems a good approach
• One module/bit
• Final module for E

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Design for MX module

• Logic function in book is
• Id call this not E, but
• Can implement as

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Design for ME module

• Final E is 1 only if all intermediate values are
  0
• So
• And a design is

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Hierarchical Verilog

• We already saw example of instantiation when we
  used AND and OR gates
• Just use module name and an identifier for the
  particular instance

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Vector of Wires (Bus)

• Denotes a set of wires
• input 10 S
• Syntax is a b where a is high-order
• So this could be 01 S
• Order will matter when we make assignments with
  values bigger than one bit
• Or when we connect sets of wires
• NOTE THIS IS NOT AN ARRAY!

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DEMO

• Lets try entering the hierarchical example

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Next slides document design

• Just for your notes

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MX

• module mx(A, B, E)
• input A, B
• output E
• assign E (A B) (A B)
• endmodule

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ME

• module me(E, Ei)
• input 30 Ei
• output E
• assign E (Ei0 Ei1 Ei2 Ei3)
• endmodule

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Top Level

• module top(A, B, E)
• input 30 A
• input 30 B
• output E
• wire 30 Ei
• mx m0(A0, B0, Ei0)
• mx m1(A1, B1, Ei1)
• mx m2(A2, B2, Ei2)
• mx m3(A3, B3, Ei3)
• me me0(E, Ei)
• endmodule

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Integrated Circuit

• Known as IC or chip
• Silicon containing circuit
• Later in semester well examine design and
  construction
• Maybe processes
• Packaged in ceramic or plastic
• From 4-6 pins to hundreds
• Pins wired to pads on chip

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Bonding
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Levels of Integration

• SSI
• Individual gates
• MSI
• Things like counters, single-block adders, etc.
• Like stuff well be doing next
• LSI
• VLSI
• Larger circuits, like the FPGA, Pentium, etc.

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Logic Families

• RTL, DTL earliest
• TTL was used 70s, 80s
• Still available and used occasionally
• 7400 series logic, refined over generations
• CMOS
• Was low speed, low noise
• Now fast and is most common
• BiCMOS and GaAs
• Speed

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Catalogs

• Catalog pages describe chips
• Look at
• http//focus.ti.com/lit/ds/scas014c/scas014c.pdf
• Specifications
• Pinouts
• Packages/Dimensions
• Electrical characteristics

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Electrical Characteristics

• Fan in max number of inputs to a gate
• Fan out how many standard loads it can drive
  (load usually 1)
• Voltage often 1.8v, 3.3v or 5v are common
• Noise margin how much electrical noise it can
  tolerate
• Power dissipation how much power chip needs
• TTL high
• Some CMOS low (but look at heat sink on a
  Pentium)
• Propagation delay next

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Propagation Delay

• Max of high-to-low and low-to-high
• Maximum and typical given

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Delays

• Transport delay pure delay
• Output after a specified time
• Inertial delay
• No effect if input occurs for time that is too
  short (cant overcome inertia) smaller than
  transport delay time

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Effect of Transport Delay (blue)

• Delay just shifts signal in time

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Effect of Inertial Delay

• Blue Propagation delay time Black
  Rejection time

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Fan Out and Delay

• Practical fan out of CMOS limited by capacitance
  of input gates
• More gates driven, longer time for signal to
  change
• So delay time for CMOS affected by fan out
• Wire delay also very important
• And routing delays in FPGA

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Example using ISE

• Look at Lab 1 (tomorrow)
• Synthesis report timing prediction
• Text-based Post Place Route timing report
• View routed design
• To see where components and I/O buffers are
  located

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Today

• Design paradigm
• Hierarchical design
• Talked about real devices
• Propagation delays
• First look at how fast your circuits could work

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Next Time

• Basic combinational circuits
• Multiplexer
• Encoders
• Decoders

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Read

• Chapter 4
• Sections 3, 4, 5
• Section 4-8 covers Verilog