Clock Generation and Distribution

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Clock Generation and Distribution
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All Digital Phase Locked Loop Design and
Implementation

• The three main parts of the phase locked loop are
  still present in the ADPLL
• They are designed and constructed differently due
  to the fact that the signals that they deal with
  are different and a FPGA is digital.
• The input to the ADPLL is a digital stream
  normally from an analog to digital converter or a
  clock.

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ADPLL

• The individual components of the ADPLL will be
  broken down into their rudimentary components
  (i.e. counters, control bits, registers).
• These are the types of components that can but
  implemented on FPGA

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ADPLL
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ADPLL

• The first stage of the ADPLL is the phase
  detector
• EXOR gate
• This type of detector locks itself 90 degree
  behind the phase of the input signal

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locked state
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Two drawbacks

• it has a phase error limit of or - 90
• it is not sensitive to edges in the signal but
  rather the flat section

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ADPLL

• An edge triggered phase detector.
• This device is an edge triggered JK device.
• Its locked state is 180 degrees behind the phase
  of the input signal as shown below.

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ADPLL
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ADPLL
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ADPLL

• This device can be used in conjunction with a
  counter to output the phase error.

fin
fout
N
Mfin
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ADPLL

• In the configuration shown above, the fin and
  fout are binary values.
• The MFin is an integer multiple (M) of the
  reference signal Fin.
• The counter is reset on the rising edges of U0
  and is gated when the output of Q is logic 1.
• The output N of the counter is proportional to
  the phase error.

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ADPLL-loop filter

• The loop filter that always works with the EXOR
  and the edge triggered phase detectors is the K
  counter

Carry
K Clock
Carry UP/DN
Borrow
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DCO

• The final part of the loop is the DCO (digitally
  controlled oscillator). In a digital system, the
  oscillator is a modified counter

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DCO

• The DECR and INCR inputs are the carry and borrow
  outputs from the K counter respectively.
• This part of the loop operates in conjunction
  with a divide by N counter that works to slow
  down this accelerated clock. The 2NFc input is
  the center frequency of the loop (Fc) multiplied
  by 2N where N is the variable in the divide by N
  counter

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DCO
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• This loop filter contains two separate counters
  both of which are counting upward.
• The UP/DN bit determines which counter is running
  at any moment.
• The K clock is MF0 where M is a large integer
  (8, 16, 32) of the reference signal Fin.
• The carry and borrow outputs are the most
  significant bits of the counters and are only
  high when the contents of a particular counter
  are greater than K/2.
• These values are used to control the DCO
  (digitally controlled oscillator). The counters
  are reset when the contents reach a value of K
  1.