TTL Characteristics

1
TTL Characteristics

• Digital Logic 1133
• Kleitz 9-3

2
TTL Sub-families

• Low Power Schottky (LS)
• as in parts kits.
• high speed
• low power consumption
• Why low power consumption important?
• conservation of energy (energy costs)
• longer portable life of batteries
• less HEAT!

3
TTL LS High Voltage

• VOH high level output voltage
• gate voltage when high
• VOH gt 2.7 volts
• VIH High level input voltage
• recognized as high level
• VIH lt 2.0 volts

4
High Level TTL LS Current

• IOH high level output current
• maximum source current
• - 400 ?A
• will not work reliably above 400 ?A
• IIH high level input current
• 20 ?A
• Thus 20 inputs can be supplied by one output.
• Fan out 20

5
Current Sign Convention

• Currents entering a gate are positive.
• Currents leaving a gate are negative.

-

6
Source Current

• Logical HIGH output current capability.

Fan Out
X 1
Source Current
7
Source Current

• Cannot source enough current to power an output.
• Need about 15 mA for an LED.
• High output current is only 0.4 mA.
• Need a driver circuit.

8
TTL LS Low Voltage

• VOL low level output voltage
• gate voltage when low
• VOL lt 0.4 volts
• VIL Low level input voltage
• recognized as low level
• VIL lt 0.8 volts

9
Low Level TTL Current

• IOL low level output current
• sink current
• for TTL LS 8 mA
• IIL low level input current
• for TTL LS - 0.4 mA
• Thus one output can sink the current of 20
  inputs.
• Fan out 20

10
Current Summary
11
Sink Current

• Current into an output gate when the gate is in
  its low state.

X 0
Sink Current
12
74LSxx Voltage LevelsFrom figure 9-7 and table
9-4 in text.
High Level Output gt2.7 V
Recognizable High Level Input gt 2.0 V
Noise Margin
Uncertain Region
Low In lt 0.8 V
Noise Margin
Low Out lt 0.4 V
13
Open Collector Output
V

• Collector is not connected to V.
• Device to be powered is inserted between
  collector and V.
• Typical driver circuit for logic.

External Load
Control
14
Sink Current
Current passes through load (an LED here), into
the gate output to the power supply ground.
15
Pulse Time

• Rise time
• time required for voltage to change from low to
  high level
• Fall time
• time required for voltage to change from high
  level to low level
• Propagation Delay
• time to move through circuit.

16
Rise Time

• The time required for a digital pulse to rise
  from 10 up to 90 of its maximum value.

17
Fall Time

• The time required for a digital pulse to fall
  from 90 down to 10 of its maximum value.

18
Propagation Delay

• Different times for transition from low to high
  and high to low.
• How long does it take to reach a set voltage?

Input
Output
tPHL
tPLH
19
Propagation Delay Example

• Similar to Text 9-10.
• Use 74LS00 NAND and 74LS002 NOR.
• Ignore rise and fall times.

20
Propagation Delay Example

• See datasheet.
• 74LS02
• tPLH
• 10 ns, typical
• 15 ns, maximum
• tPHL
• 10 ns, typical
• 15 ns, maximum

• See datasheet.
• 74LS00
• tPLH
• 9 ns, typical
• 15 ns, maximum
• tPHL
• 10 ns, typical
• 15 ns, maximum

Use Maximum ? worst case.
21
Propagation Delay Example
Cp V1 V2
15
15
30
30
If delay is longer than time clock is high (or
low) ? error occurs. Minimum clock period 2 x
30 ns 60 ns. Maximum clock frequency 1/16ns
16 MHz