CMOS RFIC Design

1
CMOS RFIC Design for Direct Conversion Receivers
Zhaofeng ZHANG
ELEC, HKUST
2
Outline of Presentation

• Background Introduction
• Design Issues and Solutions
• A Direct Conversion Pager Receiver
• Conclusion

3
Research Goal

• Low Cost
• Process CMOS
• Device is good enough
• Improved passive components
• Integration level
• Minimize external components
• Minimize IC area and pin numbers
• Low Power
• High integration low power
• Low power individual block design
• System architecture is important

SOC
4
Heterodyne Receivers

• High IF more than 2 down-conversions
• Best sensitivity
• Need off-chip image-rejection SAW filters and
  channel-selection filters
• Highest cost, high power, low integration
• Low IF
• Relaxed image-rejection requirement compared to
  high-IF
• No DC offset problem
• Quadrature LO is required
• Flicker noise may be a problem
• High integration level, low cost

5
Homodyne Receivers
Pros
Cons

• Simple architecture
• No image problem
• No 50ohm interfaces
• High integration level
• Lowest cost, low power

• DC offsets
• Flicker noise
• LO leakage
• Even-order distortion

6
Origin of Problem

• DC offsets
• Flicker noise
• LO leakage
• Even-order distortion
• Linearity requirement
• Noise requirement
• IQ mismatch

All problems are limited by the mixer design!
The mixer the most critical component!
Our research focus!
7
DC Offsets LO Leakage

• The offset originates from self-mixing.
• It can be as large as mV range at the mixer
  output.
• It varies with the environment and moving speed
  of
• the mobile and changes with time.
• The maximum bandwidth can be as large as kHz
  range.
• LO leakage forms an interference to other
  receivers.

8
Spectrum Illustration
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Existing Solutions on DC Offset

• AC coupling or high pass filtering
• Autozeroing or double sampling
• Offset cancellation in digital domain
• Double LO frequency method ISSCC99
• Adaptive dual-loop algorithm combined with the
  mixer RAWCON00
• Pulse-width-modulation based bipolar harmonic
  mixer CICC97

However, these methods are either not so
effective or too complicated, or not suitable for
CMOS process.
10
Proposed Harmonic Mixing
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Square-law Based Mixer

• LO leakage free.
• Ideally self-mixing free.
• Current controlled switching.
• No noise contribution from LO stage.

12
Flicker Noise Reduction
Vrf

• Flicker noise is proportional to the current.
• Current injection is used to reduce flicker
  noise.
• No noise contribution from current source too.

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Offset Cancellation
20
TSMC0.35?
10
gt35dB
0
-10
Gain (dB)
-20
-30
-40
-22
-20
-18
-16
LO Input Power (dBm)
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Noise Performance
60
50
40
Noise Figure _at_ 10kHz (dB)
30
20
400
600
800
1000
Injected Current I0 (?A)
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How to improve more?

• However, flicker noise is still too large due to
  CMOS devices, minimum noise figure achieved is
  larger than 24dB _at_ 10kHz for CMOS harmonic mixer.
  It requires a high gain and low noise LNA to
  overcome flicker noise while the front-end
  linearity suffers.
• For a narrow-band communication system such as
  FLEX pager, the noise requirement at low
  frequency is very tough.
• It is well known that bipolar device is a good
  candidate to eliminate flicker noise.
• But, can we do it in a CMOS process and how good
  is the device? YES!

16
Lateral Bipolar Transistor in a Bulk CMOS Process
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Physical Model of LBJT
18
Gummel Plot of LBJT
TSMC0.35?
?gt40 at mAs max fT ?4GHz
19
LBJT Harmonic Mixer
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Noise Performance
Large LO improves noise.
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Even Order Distortion
a1xa2x2a3x3
f1
f2

• It is mainly introduced by layout asymmetry and
  device mismatch.
• Since direct-conversion, the intermodulation
  components IM2 will fall into the demodulated
  signal spectrum.
• Therefore, good IIP2 is required for homodyne
  receivers.
• It is found that varying the loading resister or
  voltage bias can compensate the device mismatch
  and improve IIP2 significantly.

22
IIP2 Improvement
Same DC bias
Compensation
IIP218dBm
IIP2gt40dBm
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LBJT Mixer Performance
Technology TSMC 3M2P 0.35?m
VDD 3V
Signal Gain 15dB
DC offset suppression gt30dB
Noise figure _at_ 10kHz lt18dB
1dB compression point gt-20dBm
Input-referred IP3 gt-9dBm
Input-referred IP2 gt40dBm
Power consumption lt2.2mW
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Summary on Mixer

• Flicker noise free, corner frequency is below
  10kHz.
• DC offset free, more than 30dB DC offset
  suppression is achieved.
• No LO leakage problem.
• Sufficient IIP2 after bias compensation.
• High gain and low power consumption.
• Complete CMOS process.
• Suitable for CMOS direct conversion applications.

25
Difficulties in FLEX Pager
-1
High pass effect
BER _at_ 12dB Eb/N0
-2
10
High pass corner (Hz)
Big Challenges

• Narrow band modulation
• Significant energy near DC
• High pass filtering is not viable
• DC offset problem
• Flicker noise is significant

DC Offset Effect
BER
4
8
12
16
Eb/N0 (dB)
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4-FSK Pager Receiver
RF Zhaofeng BB Zhiheng

• Fully differential architecture to reject
  substrate noise.
• Harmonic mixers are used to solve time-varying
  DC offset.
• Peak detectors are used to cancel static DC
  offset.
• High front-end gain and current injection to
  reduce flicker noise.

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LNA

• Non-quasi-static phenomenon makes it unnecessary
  to do on-chip matching.
• Off-chip matching by a single inductor and a
  balun.
• S11lt-20dB _at_ 930MHz
• Both on-chip and off-chip inductive loads were
  tried.

28
Double Balanced Mixer
Improve the linearity Provide constant impedance
to LNA Current injection provides more than 20dB
flicker noise reduction.
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Ring Oscillator
Half RF frequency, Provide 45? phase.
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Static DC Offset Cancellation
Peak Detector
Fmin?200Hz
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Performance Summary
32
Die Photo
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Summary on Pager Receiver

• Feasibility of direct conversion has been
  demonstrated.
• Proposed harmonic mixing technique solves
  self-mixing induced DC offset problem
  successfully.
• With the help of static DC offset cancellation,
  the total DC offset is less than 1mV at the
  receiver output.
• The modified ZIFZCD 4-FSK demodulator functions
  correctly.
• A 4-FSK FLEX pager receiver in a single chip has
  been implemented successfully.

34
Conclusion

• Circuit design for direct-conversion has been
  discussed.
• DC offset more than 30dB improvement
• LO leakage no longer a problem
• Flicker noise corner frequency is less than kHz
  due to lateral bipolar device.
• IIP2 larger than 40dBm after bias compensation.
• System on chip has been successfully demonstrated
  using CMOS direct conversion architecture.