MORPHEUS project presentation 4S meeting

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MORPHEUS project presentation4S meeting
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The MORPHEUS IP project
Integrated Project IST 027342
Partners THALES (F) DEUTSCHE THOMSON (G) INTRACOM
(GR) ALCATEL / LUCENT (G) THALES OPTRONIQUE
(F) STMICROELECTRONICS (I). PACT (G) M 2000
(F) ACE (NL). CRITICAL BLUE(GB) UNIV. KARLSRUHE
(G) TU DELFT (NL) CEA (F) UBO (F) TU Braunschweig
(G) TU Chemnitz (G) ARCES- UNIVERSITA DI BOLOGNA
(I) ARTTIC (F)
Coordinator Gilbert Edelin Thales Research
Technology France
EU funding 8 200 000 Euro Duration 36
months Start date 2006-01-01
Projects website www.morpheus-ist.org
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Why Morpheus?

• Why reconfigurable platforms ?
• When performance versatility are critical
• Eg Telecommunication Networks, High Definition
  Video
• When the environment is extremely restrictive
  computing density
• Eg Wireless communication systems
• When autonomy and adaptivity are paramount
• Eg Systems for Intelligent cameras
• with minimization of system costs and time to
  market
• MORPHEUS ambitions to be the key project in
  Europe to validate these capabilities on real
  applications

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Objectives and Challenges

• Project objectives
• Productivity
• Flexibility
• Performance
• Transposition to the workplan challenges
• A test-chip defined and validated through
  applications in term of
• Modular Architecture heterogeneous grain,
  homogeneous programming model, NOC, powerful DDR
  interface
• Full range of integrated programming tools
  software based accelerator management, RTOS for
  dynamic reconfiguration, spatial design
• A reasonable area, cost effective foundry access
• A key role in increasing the awareness of the
  community about the capabilities of RC computing
  through the platform
• Exploration of the business chip level, tools,
  Ips, applications

An enabling solution for flexible  Domain
focused platforms 
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The Innovation in Morpheus

• Integration of heterogeneous modules
• ARM based platform infrastructure
• improved by the addition of a NOC (ST)
• gt a framework for the efficient integration of
  RC modules and supporting the different
  constraints of the applications (throughput,
  memory,etc)
• State of the art complementary dynamically
  reconfigurable modules
• Highly flexible fine grain generated FPGA M2000
  
• Mixed grained configurable data path exploiting
  ILP PiCoGA
• Coarse grain data flow oriented fabric PACT XPP
  with extensions towards high performance control
  flow oriented applications
• A consistent set of application development tools
  
• Masking the heterogeneous platform to the user
  high level of abstraction
• Providing a merge of HW centric and SW centric
  design flows
• Covering design/ implementation/ validation/
  debug

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The European context of Morpheus (1)

• Position in the FP6 call 4
• Morpheus is the IP on Design selected in the call
  4 (Nanoelectronics) devoted to Reconfigurable
  Computing
• European level partnership, opening real
  clustering opportunities
• Reconfigurable Computing already addressed in FP5
  and FP6 by Streps AMDREL, RECONF, 4S (FP6)
• Advanced Computing Architectures (FP6 call 4)
• FET projects in Advanced Computing Architectures
  
• Clustering in dissemination on progress with
  AETHER, SHAPES, SARC SoC design projects (FP6
  call 4) SPIRIT, others?
• More recently
• (FP6 call 5, Embedded Systems) hArtes IP project
  
• design on heterogeneous platform, scalable
  architecture
• (FP7 Strep) CRISP RC for low power

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The European context of Morpheus (2)
FET Advanced Architectures
SARC Scalable Computer Architecture
SHAPES
Embedded Systems
THALES
TU Delft, ST, THALES
AETHER Self-adaptive pervasive Computer
Architecture
CEA, THALES
hArtes
TU Delft, THOMSON, THALES
Interactions, Dissemination, Training
Standards
Toolset for heterogeneous RC platforms
SPIRIT
MORPHEUS
ST
CRISP
Low power, data flow
THALES
Tools for Dynamic Reconf on FPGA
Improved XPP, NoC, Run time
Applications, tools requirements
Reconfiguration for Intelligent cameras
PACT XPP Tech, UK, THALES
CEA, THALES
INTRACOM, ST
RECONF
4S
FP5, MEDEA
AMDREL
PICS
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Project activity status

• Tools (V1)
• Integration on-going
• Revised specification on-going
• Architecture
• Architecture defined (NOC and DDR interface added
  wrt initial Workplan)
• Architecture modeled (HDL database)
• System-C simulator on-going
• Extended simulator under discussion (phase 2)
• Implementation
• New workplan in place (CMP instead of direct ST
  foundry)
• Verification and P R on-going
• Application test cases
• Phase 1 reference platforms implemented (Intracom
  still on-going because of redefinition)

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Overall MORPHEUS Work Package organisation
WP2
WP2
DTB
WP1
WP3
Methodologies
Methodologie
Management

Architecture

tools

tools

TRT
ARTTIC
(TRT)
WP4
Platform
ST
integration
monitoring

RTD
Intracom
activities
Demonstration
WP5
activities
Application
WP7
test cases
Demonstration

Management
and validation

activities
UK
Training
activities
WP6
WP8
Exploitation

Training
dissemination
ST
6A1, page 25
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The targeted markets (1)

• Four domains of applications

Ex 2 A Multihop Wireless Network IEEE 802.16
Ex 1 A HD video/digital film processing unit
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The targeted markets (2)

• Contd

Ex 3 Intelligent cameras
Ex 4 Telecommunication Network
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MORPHEUS chip architecture
ARM/AMBA Subsystem (control/infrastructure)
S
S
ETM
ETM
-
-
ITCM
ITCM
IRQ
IRQ
FIQ
FIQ
ARM926EJ
ARM926EJ
Proc.
Proc.
DTCM
DTCM
FIQ
DMA
-
-
ROM
Co
Co
REG
S
S
IM
DM
Main AHB
S
S
DS
S
DS
DS
CS
CS
CS
S
S
S
XR
DEB
XR
DEB
2
3-level memory subsystem
NoC
PiCoGA
PACT
CEB
CEB
M
S
S
S
S
M
S
S
M
REG
DMA
FIQ
high speed interconnect (Spidergon
network-on-chip)
fine grain
coarse grain
mid grain
(re-)configuration support
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WP2 toolset flow overview
Annotated C code of global application
C language sub-functions library
Compiler and OS jointly manage task accelerations
Spatial Design (function graphical capture and
synthesis)
RTOS Dynamic control library
Hardware Information File
Molen compiler
Spatial Design generates configurations including
SOC communications
Formal specification
Application code
OS code
Reconfigurable functions configuration code
EDIF, NML, Griffy-C
HRE IP tools
ARM host processor, DMA, DNA, Prog. memory
Reconfigurable Units Config. Memory
VHDL, Xilinx Jbit/XVFS,
FPGA tools and other design and verification tools
Configuration Manager
SystemC model (phase 1) in Coware ModelDesigner
MORPHEUS PO Meeting, Brussels, 16.11.2007
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Potential Impact

• Strategic a first step toward a new generation
  of Embedded Computing Platforms
• Domain focused platforms based on  Soft HW 
  architectures
• Economical market opportunity
• eFPGA market from 10.9 million in 2003 to over
  807.4 million by 2008 (CAGR 137, In-Stat/MDR
  Oct 04)
• Tools a new generation of System level
  Co-design tools with a SW oriented Design Flow
  addressing parallel computing
• Exploitation plans
• Silicon platform major ambition of the project
• Target Market on-going refinement (business
  model, business plan) ST
• HW Ips (building blocks) exploitation of the
  demonstrated developments within the project.
• Tools
• The mid and low level tool strictly required for
  making the reconfigurable platform usable
• SME as tool providers on an extending market
• Industrial use and benefits
• Ensure a sustainable embedded computing platform
  in Europe
• Provide performance and productivity

5.1, pages 18-
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In summary

• A multipurpose Silicon demonstrator with dynamic
  reconfiguration capabilities
• Complying with a broad range of applications
• Integrating heterogeneous existing RC structures
  inserted into a NoC based platform supporting
  RTOS for reconfiguration
• An integrated Design Toolset addressing both
  architecture development (spatial design) and
  application development (mainly data intensive)
  on the target architecture
• Using the elementary tools of the RC blocks
  plugged in a seamless system level programming
  environment retargetable compilation, dynamic
  scheduling, architecture synthesis, formal
  methods
• Generic tool chain starting from system-level
  specifications with architectural exploration
  capabilities, demonstrated on the Morpheus
  platform

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THALES involved in Reconfigurable Technologies

• A large panel of RT projects
• European projects
• MORPHEUS FP6 IP (THALES RT, coord.) focuses on
  tools (for application development productivity),
  dynamic reconfiguration (for computation
  density), interconnect hardware, middleware and
  tools (for scalability), heterogeneity (for
  multi-domain usage)
• AETHER FP6 FET (THALES RT) focuses on
  self-adaptive architecture and associated tools
  (for pervasive applications, application
  development productivity)
• 4S FP6 STREP (THALES Com. )
• HARTES FP6 IP (THALES Com. ) focuses on tools,
  Thales more precisely on operating systems
• CRISP FP7 STREP (THALES Air Syst - NL) based on
  Recore / Montium
• RECOPS (THALES Com. Fr, Be, I) Eurofinder
  project on reconfiguration usage and partial
  reconfiguration
• ANDRES (THALES Com.) Run-time Reconfigurable
  heterogeneous Systems (Thales with user role)
• National projects
• FOSFOR Agence Nationale de la Recherche (THALES
  RT), dynamic reconfiguration
• TER_at_OPS Pôle System_at_tic (THALES RT), MPSOC
  including reconfiguration tech.

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THALES strategy in Reconfigurable Technologies

• Needs beyond FPGA, toward a programmable
  solution
• Processing towards coarse grain, dynamic
  reconfiguration
• high performance density flexibility
• Tools
• streaming (TRT background)
• accelerator management (currently with Delft
  partnership)
• dynamic reconfiguration management (currently
  with Karlsruhe, Cergy)
• System architecture
• perennial scalable platform (NOC, communication
  management),
• Reconfigurable IP
• heterogeneity (combination of fine and coarse
  grain)
• experience with PICOGA, MONTIUM, PACT, M2000
• Applications
• multi-domain (video, radio, ...)
• small quantity
• Future studies
• Insertion in MPSOC reconfigurable accelerators
  enabling flexibility in processing nodes (for
  example data formats flexibility) and IOs
  (protocols flex.)
• Insertion in high performance computing
• Utilisation for yield improvement and reliability
  combined with performance