Presentazione di PowerPoint

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SDD DAQ CARLOSrx
INFN Bologna Samuele Antinori Davide
Falchieri Alessandro Gabrielli Enzo Gandolfi
Massimo Masetti
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Bologna
Torino
Final SDD DAQ chain 24 CARLOSrx
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busy
LTU
TTCrq
TTCvi
TTCex
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CARLOSrx

DRORC
12
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CARLOSrx logic architecture
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DESER
REC
LOGIC
FIFO
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DESER
REC
LOGIC
FIFO
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DESER
REC
LOGIC
FIFO
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DESER
REC
LOGIC
FIFO
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DESER
REC
LOGIC
FIFO
queue manager event builder
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data from 12 CARLOS
DESER
REC
LOGIC
FIFO
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SIU
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16
DESER
REC
LOGIC
FIFO
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DESER
REC
LOGIC
FIFO
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DESER
REC
LOGIC
FIFO
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DESER
REC
LOGIC
FIFO
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DESER
REC
LOGIC
FIFO
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DESER
REC
LOGIC
FIFO
clock serial link for 12 CARLOS
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serial link
VME64x
24 TRANSM
LOGIC
LOGIC
ck
L0, L1, L2
TTCrx QPLL
TTC
busy
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CARLOSrx tasks

• What shall CARLOSrx do ?
• high bandwidth data concentration and buffering
• from 12 CARLOS end ladder boards to 1 DDL
• 12 x 640 Mbit/s in input, 1.28 Gbit/s in output.
• error checking and status monitoring
• clock distribution and build the busy signal
  towards the LTU
• program the front-end chips when receiving the
  related command from the SIU and when some errors
  occur.
• Data buffer capacity
• A SDD event is 128 Kbytes without compression
• The same event takes 7 Kbytes with compression
• CARLOSrx has a buffer gt 256 Kbytes per channel

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Final CARLOSrx board design

• Each CARLOSrx board has to manage
• 12 optical fibres (800 Mbit/s) from 12 SDD end
  ladders ? data
• 12 optical fibres (80 Mbit/s) towards the SDD end
  ladders ? clock
• 12 optical fibres (40 Mbit/s) towards the SDD end
  ladders ? serial link
• TTCrq interface ? timing trigger information
  (including L0)
• SIU interface ? front-end config and data
  transmission
• VME interface ? loading firmware into on-board
  PROMs
• LTU interface ? busy signal

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May 05 first CARLOSrx design (one 6U board)
Layout scheme presented at ITS week in May 05
where it was foreseen to use the
parallel optical receiver / transmitter for 12
optical fibres from NGK electronics
BUT
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June 05

• PROBLEM No parallel optical transceiver was
  available any longer on the market.
• SOLUTION Single optical transceivers have to be
  used.
• PROBLEM 24 optical transceivers cannot be hosted
  on only one VME board.
• SOLUTION CARLOSrx breaks in 2 9U PCBs
• CARLOSrx for data processing
• CARLOSrx for clock distribution

BUT the deadlines shift because the realisation
is much more sophisticated
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CARLOSrx for data processing
40 MHz
80 MHz
80 MHz
80 MHz
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16
DESER
TRANSC
XC2VP20
R
FIFO
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32
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16
DESER
TRANSC
FIFO
R
FIFO
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16
DESER
TRANSC
FIFO
R
72T36125
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16
FIFO
R
DESER
TRANSC
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16
16
32
FIFO
R
FIFO
DESER
TRANSC
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16
FIFO
R
DESER
TRANSC
32
1 MB
SIU
40 MHz
FIFO
80 MHz
DESER
TRANSC
16
16
40 MHz
FIFO
R
100 KB
DESER
TRANSC
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32
16
16
FIFO
R
FIFO
DESER
TRANSC
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16
FIFO
R
DESER
TRANSC
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16
72T36125
R
FIFO
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16
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DESER
TRANSC
FIFO
R
FIFO
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16
DESER
TRANSC
FIFO
R
serial link
L0, L1 L2
XC2VP7
clock
TTCrq
TTC
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CARLOSrx for data processing

• 9U x 400 mm PCB
• 12 Optoway optical transceivers for I/O (dealing
  with 24 I/O fibers)
• 3 Virtex II PRO FPGAs
• 1 Spartan II FPGA
• Link to the SIU
• 12 internal bus, each 16 bit at 40 MHz
• Power consumption
• 6 A from 5V
• 8A from 3.3V

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data
dataflow
TTCrq
SIU
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trigger distr.
serial link
SIU
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clock distr.
clock
SIU
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JTAG distr.
serial link
TTCrq
SIU
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VME control
TTCrq
SIU
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CARLOSrx for clock distribution
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Foreseen CARLOSrx test setup
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CARLOSrx test
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CARLOSrx test
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VME crate
Delivery date 1 Feb 2006
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VME crate
Card-Cage Wiener 0B06.021JK Vario Local
4x6U, 17x9U, FT400mm Total Height 11U
Backplane VME64x 6U slots 4 Power
supply Wiener 0P06.0720 6U (5V/200A,
3.3V/100A, 12V/10A) Cooling air Control
CANbus Fan-tray Wiener 0F00.070A 9U FM (400mm)
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Boards disposition in the VME crate
CARLOSrx CLOCK
CARLOSrx
FANIN
CPU
CARLOSrx CLOCK
CARLOSrx CLOCK
CARLOSrx CLOCK
CARLOSrx CLOCK
CARLOSrx CLOCK
CARLOSrx
CARLOSrx
CARLOSrx
CARLOSrx
CARLOSrx
CARLOSrx CLOCK
CARLOSrx CLOCK
CARLOSrx
CARLOSrx
empty
empty
empty
6 U
9 U
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Work plan in Bologna
End November 2005 PCB final design submission
for CARLOSrx data processing, while CARLOSrx
clock will be delayed if the clocks have to be
shifted with programmable steps. January 2006
Start of the test of the prototype with the two
boards linked together inside the crate. March -
April 2006 Start of the production if the test
is OK.
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