Interconnect/Via

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Interconnect/Via
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Delay of Devices and Interconnect
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Reduction of the feature size
The difference in the arrival times of the clock
signal to all registers in a synchronous digital
system
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An Example , The Clock Distribution Network
(CDN)
A set of interconnections that delivers reliably
a time reference, clock signal , to every
register element in a synchronous digital system.
PowerPC microprocessor 32,000 master/slave latch
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Power Consumption Routing and system complexity
P CV2f
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Delay model of the CDN, Elmore Delay model
It takes into account the interconnect resistance
and capacitance and the capacitance of the
registers
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Example Routing delay problems The Clock
Skew
The difference between time arrivals of the clock
signal to all the registers in a synchronous
digital system
S(ij) Ti - Tj
Two conditions
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Minimizing the effects of delay, The H_Tree
If it is possible to divide the set of registers
R into two symmetric sets recursively and
alternatively by vertical and horizontal lines,
then the set R can be connected by an H-tree
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Interconnect Length
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Interconnect/Via
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Cross Section View of Capacitances in interconnect
Units are in Angstrom, 1A0.1nm
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Interconnect
Interconnects in chips are routed in several
layers horizontally and vertically and used
according to their application
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Parallel and fringing Capacitance
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Fringing Capacitance
T is the thickness of wire H is the distance of
wire to substrate.
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Cross Talk
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Fringing/ Parallel Plate Capacitance of
Interconnect
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Modeling Interconnect
LUMPED MODEL
T-MODEL
-MODEL
2T-MODEL
2p -MODEL
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Modeling of Interconnect
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Delay of Interconnect
Capacitance C/unit area L (length) W
(width) C
Resistance R/ number of squares R
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Delay comparison
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Example
A signal is propagated on a 6mm length metal 1
(M1) interconnect of CMOSIS5 Process, using
minimum wire width. Calculate the delay and
comment on methods for reducing this delay.
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Different Path
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Thank you !
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What is the maximum size of silicon chip?

• Power dissipation
• Packaging
• Number of pins
• Technology
• The interconnect
• used

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Inductances
For die wires
h is the height of the wire above the
substrate, d is the diameter of the wire is
the magnetic permeability of the material
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Inductance
For on-chip,
h is the height of the wire above the
substrate, d is the diameter of the wire is
the magnetic permeability of the material
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Example on VDD Bounce
Determine the values of due to
inductive and resistive losses when the output
driver sources 10mA in 1.5ns in the following
circuit.
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Example on Power lines
What will be the power line width if you drive a
10pF load at 1GHz Assume Vdd3.5V.
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Example on Charge Sharing
Calculate the drop in voltage for 64 read lines
each consisting of 0.1pF capacitances. Assume
bus capacitance to be 10pF.
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Thank you !