Diapositiva 1

1
Tools for Discovery
Digital Pulse Processing for Physics
Applications Ganil 2 February 2011 Carlo Tintori
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Outline

• Description of the hardware of the waveform
  digitizers
• Overview on the CAEN Digitizer family
• Use of the digitizers for physics applications
• Comparison between the traditional analog
  acquisition chains and the new fully digital
  approach
• DPP algorithms
• Pulse triggering
• Zero suppression
• Pulse Height Analysis
• Charge Integration
• Gamma-Neutron discrimination
• Time measurement
• Multi Channel Scaler

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Digitizers vs Oscilloscopes

• The principle of operation of a waveform
  digitizer is the same as the digital
  oscilloscope when the trigger occurs, a certain
  number of samples is saved into one memory buffer
  (acquisition window)
• However, there are important differences
• no dead-time between triggers (Multi Event
  Memory)
• multi-board synchronization for system
  scalability
• high bandwidth data readout links
• on-line data processing (FPGA or DSP)

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Highlights

• VME, NIM, PCI Express and Desktop
• VME64X, Optical Link (CONET), USB 2.0, PCI
  Express Interfaces available
• Memory buffer up to 10MB/ch (max. 1024 events)
• Multi-board synchronization and trigger
  distribution
• Programmable PLL for clock synthesis
• Programmable digital I/Os
• Analog output with majority or linear sum
• FPGA firmware for Digital Pulse Processing
• Software for Windows and Linux

• From 2 to 64 channels
• Up to 5 GS/s sampling rate - Up to 14 bit
• FPGA firmware for Digital Pulse Processing

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Digitizers Table
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Architecture
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Digitizers for Physics Applications

• Traditionally, the acquisition chains for
  radiation detectors are made out of mainly analog
  circuits the A to D conversion is performed at
  the very end of the chain
• Nowadays, the availability of very fast and high
  precision flash ADCs permits to design
  acquisition systems in which the A to D
  conversion occurs as close as possible to the
  detector
• The data throughput is extremely high it is no
  possible to transfer row data to the computers
  and make the analysis off-line!
• On-line digital data processing in needed to
  extract only the information of interest (Zero
  Suppression Digital Pulse Processing)
• The aim of the DPP for Physics Applications is to
  provide FPGA algorithms able to make in digital
  the same functions of analog modules such as
  Shaping Amplifiers, Discriminators, Charge ADCs,
  Peak Sensing ADCs, TDCs, Scalers, Coincidence
  Units, etc.

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Traditional chain example 1charge sensitive
preamplifiers
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Traditional chain example 2trans-impedance
(current sensitive) preamplifier

• The QDC is not self-triggering need a gate
  generator
• need delay lines to compensate the delay of the
  gate logic

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Benefits of the digital approach

• One single board can do the job of several analog
  modules
• Full information preserved
• Reduction in size, cabling, power consumption and
  cost per channel
• High reliability and reproducibility
• Flexibility (different digital algorithms can be
  designed and loaded at any time into the same
  hardware)

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Standard vs DPP firmware

• Standard Firmware
• common trigger on all channels simultaneously
• programmable record length and pre/post trigger
• channels self trigger digital discriminator with
  programmable threshold
• multi board synchronization (clock, sync and
  trigger distribution)
• trigger time stamps
• multi event memory buffers (up to 1024 events)
• waveform mode only (raw data)
• DPP Firmware
• trigger and timing filters for pulse
  identification and triggering
• channels can trigger independently
• energy filters for the pulse height analysis
  (trapezoidal filters)
• energy filters for the digital charge integration
  (digital QDC)
• configurable event data format (time and/or
  energy and/or waveform)
• individual trigger propagation on channel basis,
  also from board to board
• pulse shape analysis (e.g. gamma neutron
  discrimination)
• event data packing for high counting rate

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Raw waveform mode vs DPP events
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Individual vs Common trigger
empty event
400 ns 100100 samples 300 bytes/event (2ch)
80 ns 20 samples 30 bytes/event
Common
Individual
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Trigger and timing filter (I)

• Pulse triggering is the basis for all DPP and
  Zero Suppression algorithms
• Fast Shaping filter RC-CRN (N1, 2)
• Immune to baseline fluctuation and low frequency
  noise (ground loop)
• Pulse identification also with the presence of
  pile-up
• High frequency noise rejection (RC like mean
  filter)
• Can operate as a digital CFD
• Zero crossing for precise timing information
• Off-line interpolation to overcome the sampling
  period granularity
• Zero crossing of CFD can also be used for rise
  time discrimination

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Trigger and timing filter (II)
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Zero Suppression

• Data reduction algorithms can be developed to
  reduce the data throughput
• Full event suppression one event (acquisition
  window) is discarded if no pulse is detected
  inside the window
• Zero Length Encoding only the parts exceeding
  the threshold (plus a certain number of samples
  before and after) are saved.

ZLE
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DPP for the Pulse Height Analysis (DPP-TF)

• Digital implementation of the shaping amplifier
  peak sensing ADC (Multi-Channel Analyzer)
• Charge sensitive preamplifier directly connected
  to the digitizer
• Implemented in the 14 bit, 100MSps digitizers
  (mod. 724)
• Use of trapezoidal filters to shape the long tail
  exponential pulses
• Pile-up rejection, Baseline restoration,
  ballistic deficit correction
• High counting rate, very low dead time
• Energy and timing information can be combined
• Best suited for high resolution spectroscopy
  (HPGe and Si detectors)

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DPP-TF Block Diagram
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Example of trapezoidal filter output
Trapezoid Height Energy
Pile-up
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DPP-TF / Analog Chain set-ups
N1470High Voltage
N968 Shaping Amplifier
N957 Peak Sensing ADC
Energy
C.S. PRE
Ge / Si
DT5724 14bit _at_ 100MSps Digitizer DPP-TF
Energy
Time
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High Rate spectroscopy (DPP-TF)

• Rise Time Discriminator (RTD)
• Detection of pulses piling-up on the rising edge
• Cancellation of the sum peaks
• Pulse count rate correction (true rate)
• Baseline Restorer
• Programmable number of points for the BL
  calculation
• Programmable hold-off for a better BL recovery
• Constraints on the pulse separation

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22
DPP-TF Test Results with CdTe
70 KHz
200 KHz
Sum Peaks with and withou RTD
800 KHz
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23
Dead Time (DPP-TF)

• Dead-timeless acquisition (no conversion time)
• Double pulse resolution ? Rise Time (two pulses
  separated by at least the rise time can be
  distinguished)
• The rise time discriminator allows double pulses
  piling up on the rising edge to be detected and
  counted twice
• Although pile-up causes the loss of some
  energies, the DPP-TF is able to get the
  timestamps of nearly all pulses true rate can be
  calculated
• Residual multiple pulses that cannot be
  distinguished (despite the RTD) can be taken into
  account on a statistical basis
• Histogram (spectrum) calculated off-line easy
  implementation of techniques for the dead-time
  correction (loss of energy counts)
• The number and the position of lost counts is
  known they can be dynamically re-distributed on
  the histogram. This is very important in the
  cases where the activity is not constant in time.

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Individual inter-channel triggering (DPP-TF)

• Mainly needed in segmented (cloves) detectors
• One channel triggers itself and also neighbour
  channels
• Individual TRG-IN and TRG-OUT lines from each
  channel to the Front Panel GPIO connector (8
  inputs 8 outputs)
• External trigger unit (V1495) for the coincidence
  matrix implementation
• Can work also between cards
• Available in the new DPP-TF (724 series)
• Can be implemented in the 720 and 751 series as
  well

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Pulse Shape Analysis (DPP-TF)

• Some applications need to perform pulse shape
  analysis to validate or correct the
  energy/timestamp information
• Usually a small set of samples (short waveform)
  is required for the DPP-TF, this is typically
  the rising edge
• Unlike the oscilloscope like acquisition mode,
  the recording of this waveform chunk has a little
  overhead in the readout rate
• Also used to improve the timestamp resolution
  just two samples around the CFD zero crossing
  linearly interpolated off-line permit to make the
  resolution up to 100 times better than sampling
  period

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DPP-TF Test Results

• Germanium Detectors at LNL (Legnaro - Italy) in
  Nov-08 and Feb-09, at GSI (Germany) on May-09, at
  INFN-MI on Jan-10, in Japan on Feb-10, at Duke
  University (USA) on Jul-10 Palermo on Jan 2011
  resolution 1.98 KeV _at_ 1.33 MeV (60Co)
• Silicon Strip (SSSSD and DSSSD) and CsI detectors
  in Sweden at Lund and Uppsala (ion beam test)
• CdTe at high rate (up to 800KHz) for spectroscopy
  imaging
• NaI detectors in CAEN (see demo)
• PET in U.S.A.
• Homeland security application using CsI
• BGO detector at ENEA Centro Ricerche Casaccia
  (Rome)

60Co with Ge
228Th with DSSSD
FWHM _at_ 1.33 MeV 1.98 KeV
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DPP for the Charge Integration(DPP_CI)

• Digital implementation of the QDC discriminator
  and gate generator
• Implemented in the 12 bit, high speed digitizers
  ( Mod. 720() )
• Self-gating integration no delay line to fit the
  pulse within the gate
• Baseline restoration (pedestal cancellation)
• Extremely high dynamic range
• Dead-timeless acquisition (no conversion time)
• Energy and timing information can be combined
• Coincidences can be easily applied off-line
• Typically used for PMT or SiPM/MPPC readout

() Implementation in the Mod751 is a work in
progress
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DPP-CI Block Diagram
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DPP-CI / Analog Chain set-ups
N1470High Voltage
DelayN108A
QDCV792N
Charge
Splitter A315
Dual TimerN93B
CFDN842
PMT
NaI(Tl)
TDC V1190
Time
DT5720 12bit _at_ 250MSps Digitizer DPP-CI
Charge
Time
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DPP-CI Test Results
NaI detector and PMT directly connected to the
QDC or digitizer
DPP-CI Analog QDC
Energy (MeV) Res () Res ()
0.481 (137Cs Compton edge) 9.41 ? 1.18 12.80 ? 0.70
0.662 (137Cs Photopeak) 7.01 ? 0.04 8.17 ? 0.04
1.33 (60Co Photopeak) 5.67 ? 0.03 6.66 ? 0.18
1.17 (60Co Photopeak) 5.46 ? 0.02 5.89 ?0.13
2.51 (60Co Sum peak) 3.82 ? 0.11 4.10 ? 0.24
Resolution FWHM 100 / Mean
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DPP-CI Other Tests

• Tested with SiPM/MPPC detectors at Univerità
  dellInsubria (Como Italy) and in CAEN
  (2009/2010)
• Dark Counting Rate
• LED pulser
• Readout of a 3x3mm Lyso Crystal Gamma source
• Readout of a scintillator tile for beta particles

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DPP for ?-n Discrimination

• Digital implementation of the ?E/E or Rise Time
  discriminator (both are Pulse Shape Analysis)
• Digital ?E/E double gate charge integration
  (same as DPP-CI but with two gates) applied to
  fast detectors (typ. organic liquid
  scintillators)
• Digital Rise Time discrimination ?T in the Zero
  Crossing of two CFDs at 25 and 75 applied to
  integrated output (either from C.S. preamp or
  digital integrator)
• PSA used to discard unwanted events (typ.
  gammas) good events saved including waveform,
  energy and time stamp
• Dead-timeless acquisition (no conversion time)
• Algorithms tested at Duke University on July 2010
  (off-line). FPGA implementation just finished.
  Will be tested next week.

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DPP-NG vs DPP-CI

• Dual Gate
• Gate position and length settings with 4 ns
  granularity (DPP-CI has 8 ns)
• Gate position can be referred to either the
  threshold crossing or the pulse peak
• PSD parameter QSHORT / (QLONG-QSHORT) can be used
  to decide whether an event has to be saved or
  discarded
• Better baseline restoration
• Improved readout (event packing)
• Two Channel coincidence discontinued
• Need big FPGA option!

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?-n Discrimination Block Diagram (I)
Algorithms tested off-line Firmware under test
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?-n Discrimination Block Diagram (II)
Algorithms tested off-line Firmware not planned
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?-n Discrimination preliminary results (I)
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?-n Discrimination preliminary results (II)
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?-n Discrimination preliminary results (III)
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?-n Discrimination preliminary results (IV)
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DPP for Time Measurements

• Digital implementation of the TDC CFD
• DPP-TF and DPP-CI give time stamps with the
  resolution of the sampling period (10 ns and 4
  ns, ? Ts/?12) interpolation can improve timing
  resolution
• Extremely high dynamic range
• Dead-timeless acquisition (no conversion time)
  can manage long bursts of pulses (theoretical
  unlimited double pulse resolution)
• Big dependence of the resolution from the
  rise-time and amplitude of the pulses (?V/ ?T)

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41
Digital CFD and Timing Filters
NOTE the higher ZC slope and the lower tail, the
better filter
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ZC timing errors

• The timing resolution is affected by three main
  sources of noise
• Electronic noise in the analog signal (not
  considered here)
• Quantization error Eq
• Interpolation error Ei
• Both simulations and experimental test
  demonstrate that there are two different regions
• When Rise Time gt 5Ts the pulse edge can be well
  approximated to a straight line, hence Ei is
  negligible. The resolution is proportional to the
  rise time and to the number of bits of the ADC.
• When Rise Time lt 5Ts the approximation to a
  straight line is too rough and Ei is the dominant
  source of error. The resolution is still
  proportional to the number of bit but becomes
  inversely proportional to the rise time.
  Resolution improvement expected for cubic
  interpolation.
• The best resolution is for Rise Time 5Ts,
  regardless the type of digitizer
• The resolution is always proportional to the
  pulse amplitude (more precisely to the slope
  ?V/?T)

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Sampling Clock phase effect (RTlt5Ts) (I)
When rise time lt 5Ts, the interpolation error
has a big variation with the phase between the
rising edge and the sampling clock.

• DELAYAB N Ts
• same clock phase for A and B ?
• same interpolation error ?
• ERRA ? ERRB ?
• Error cancellation in calculating TIMEAB

• DELAYAB (N0.5) Ts
• rotated clock phase for A and B ?
• different interpolation error ?
• ERRA ? ERRB ?
• No error cancellation. ERRA and ERRB are
  symmetric twin peak distribution

TIMEAB (ZCA ERRA) (ZCB ERRB) ZCA ZCB
(ERRA - ERRB )
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Sampling Clock phase effect (RTlt5Ts) (II)
DELAY N Ts
DELAY (N 0.5) Ts
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Sampling Clock phase effect (RTlt5Ts) (III)
Vpp 100mV Rise Time Ts Emulation
14bit 100MSps
12bit 250MSps
10bit 1GSps
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46
Sampling Clock phase effect (RTlt5Ts) (IV)
Vpp 100mV Mod720 12bit 250MSps Emulation
5 ns
10 ns
15 ns
Rise Time
20 ns
30 ns
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47
Preliminary results Mod724
(14 bit, 100 MS/s)
DELAYAB (N0.5) Ts (worst case)
50 mV
StdDev (ns)
100 mV
200 mV
500 mV
RiseTime (ns)
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Preliminary results Mod720
(12 bit, 250 MS/s)
DELAYAB (N0.5) Ts (worst case)
50mV
100mV
200mV
StdDev (ns)
500mV
RiseTime (ns)
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Preliminary results Mod751
(10 bit, 1 GS/s)
DELAYAB (N0.5) Ts (worst case)
50mV
100mV
200mV
StdDev (ns)
500mV
NOTE the region with Rise Time lt 5Ts (5 ns) is
missing in this plot
RiseTime (ns)
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Mod724 vs Mod720 vs Mod751
Amplitude 100 mV
10 bit, 1 GS/s
12 bit, 250 MS/s
14 bit, 100 MS/s
StdDev (ns)
RiseTime (ns)
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51
Mod751 _at_ 2 GS/s
The cubic interpolation can reduce the gap
between best and worst case as well as increase
the resolution for small signals!
StdDev (ns)
RT 1 ns - worst case
RT 5 ns
RT 1 ns - best case
? ? 2 ps !
Amplitude (mV)
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DPP for Pulse Counting (SCA)

• Digital implementation of the discriminator
  scaler (Single-Channel Analyzer)
• Can be implemented in the high density digitizers
  (mod. 740)
• Pulse Triggering baseline restoration, noise
  rejection, etc
• Single or Multi-Channel Energy Windowing

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