Title: Diapositiva 1
1RPC Technical Trigger
Flavio Loddo I.N.F.N. Bari on behalf of Barrel
RPC Collaboration
2RPC Technical Trigger
Phase I Sector Trigger for testing RPC (and DT)
during Commissioning
RBC (RPC Balcony Collector)
RPC Cosmic trigger
Phase II Technical trigger to be used during
off-beam periods for RPC (and other detectors)
calibration
RBC TTU (Technical Trigger Unit)
3Block Diagram of RPC DAQ
4RPC LBBox
In Barrel LBBox it is unused It can provide the
OR of 96 strips (half RPC)
5Phase I RBC (RPC Balcony Collector) Main Features
Generic Barrel Sector
- Receive 2x13 (or 15) ORs from LB (LVDS)
- (OR of 96 strips (1 bi-gap half RPC))
- Produce Sector Trigger
- Mask noisy/dead Ors
- Force selected ORs to be in the coincidence to
- increase trigger selectivity
- Majority level selectable between 1 and 6
- I2C Interface
- Re-Transmit input OR electrically (LVDS) to TDC
- Transmit input OR optically to Counting Room (GOL)
RB4
RB3
RB2_OUT
RB2_IN
RB1_OUT
RB1_IN
6RBC Block Diagram
CMOS-LVDS Driver
FPGA (Spartan IIE)
to TDC
LVDS-CMOS converter
13 (15) ORs
Programmable Majority Logic
Trigger 1
From 2 LBBoxes
13 (15) ORs
(2 sectors)
Trigger 2
GOL
Controller
Reconf
HFE4383
( Reconfigure FPGA every 5 mins to recover
eventual SEU loss of configuration)
to Optical PP
QPLL
Deskewed HF clock
I2C (from CB)
1 RBC per 2 sectors 6 RBC/Wheel 30 RBC/Barrel
40 MHz LHC Clock (from LB)
7RBC Status
- FPGA design is under development.
- What was done
- I2C Interface
- Masking and Forcing feature
- Trigger generation (but Im waiting for further
input/suggestions from Users) - Still to do
- GOL management
- Board design .
- .
- Open issues
- Board location
- Fibers routing and patch panels
- INFN Financial approval
- .
8Phase !! RPC Technical Trigger Implementation
USC area
UXC area
1 RBC/ 2 sectors
Fiber
Barrel Wheel
10 Optical Ribbons
1 Optical Ribbon/Half wheel
9TTU (Technical Trigger Unit) Block Diagram
(Preliminary)
- Receive optical link from RBCs
- Combine ORs from 1 Wheel (or from Half Wheel)
- ..
Programmable Majority Unit
TLK2501
TLK2501
Trigger
TLK2501
TLK2501
TLK2501
HFBR782
6 Fibers
Deskewed HF clock
VME Interface
QPLL
TTCrx
Comm. line
LHC Clock
10Cost Estimation
- RBC QPLLGOLVCSEL 100,00
- FPGA 100,00
- PCB 300,00
- Various 100,00
- NRE 1000,00
- Tot (30 RBC) 20.000,00
- Fibers (6000 m) 6000,00
- 5 TTU 15000,00
- 1 VME crate 5000,00
- 1 VME controller (V2728) 3000,00