Kein Folientitel

1
C164CI Block Diagram
C166-Core
16
64 K ROM (C164 CI-8RM) or OTP (C164CI-8EM)
Data
RAM
CPU
Dual Port
Instr./Data
Data
2 KByte
32
16
PLL-Oscillator prog. Multiplier 0.5 1 1.5
2 2.5 3 4 5
Watchdog
PEC
External Instr./Data
13 ext. IR
RTC
Interrupt Controller
P4.5/ CAN RxD
Full-CAN Interface V2.0B active
16
Interrupt Bus
Peripheral Data
16
P4.6/ CAN TxD
XBUS (16-bit NON MUX Data / Addresses)
10-Bit ADC
CAPCOM6 Unit for PWM Generation
GPT1
Sync. Channel
CAPCOM 2
USART
External Bus 8/16 bit MUX only XBUS Control
T2
(SPI)
Port 0
16
8-Channel
8-Channels
ASC
SSC
Timer 13
T3
Timer 7
Timer 8
BRG
BRG
T4
1 Comp. Channel
3/6 CAPCOM Channels
Port 3
Port 5
Port 8
Port 1
Port 4
6
16
4
8
9
2
CPU Block Diagram
CPU
Exec. Unit Instr. Ptr. Instr. Reg.
MDH
SP
On-Chip Static RAM
MDL
STK OV
STK UV
4-Stage Pipeline
ALU
PSW
16-bit
SYSCON
Barrel-Shifter
BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4
Context Ptr.
SFR
3
Four stage instruction-pipeline

• 100ns effective execution time (20 MHz fCPU)
• Three Pre-Fetch-Steps in word size (Bus
  Controller) for supporting of the Pipeline
• Optimized execution of jumps
• For jump instructions (Jump, Cond. Jump, Call,
  Return,...) usually only one additional machine
  cycle is necessary, to fetch the instruction at
  the destination address
• Jump Cache
• For the execution of loops no additional machine
  cycle is necessary

4
Arithmetic Logic Unit
A
B
Logic Operations
and nand or nor exor exnor not
Cout
Cin
ALU
op
flags
Shift / Rotate
Z
Arithmetic Operations
sll srl sla sra rol ror
add sub inc dec neg
s/ro shift/rotate l/r left/right l/a logic
(unsigned)/arithmetic (signed)
5
Barrel Shifter
6
General Purpose Register (GPR)

• 16 GPRs form a register bankwhich consits of
  maximize
• 8 Word-Registers and
• 8 Word-Registers with byte access to the least
  significant and most significant byte
• The GPRs are bit-addressable
• the register banks can be arranged in the
  internal RAM in any order
• The mapping of the active register bank is
  determined by the Context Pointer (CP)
• CP can easily changed to choose an other register
  bank - Switch Context-instruction.

7
2 kByte internal RAM mapping of the register
banks and the stack
R15
2KBytes internal RAM
R14
R13
0FDFE
R12
R11
R10
R15
R9
R8
R7
RH7
R6
RH6
R5
RH5
Context pointer
R4
R0
RH4
R3
RH3
R2
0FC00
RH2
STKUV
R1
RH1
R0
RH0
Stackpointer Underflow Stackpointer Stackpointer
Overflow
STKUV
SP
STKOV
0F600
STKOV
8
Address Space

• Complete address space
• 64 kByte non-segmented address space
• Up to 4 MBytes segmented address spaces64 kByte
  Code-Segments and 16 kBytes Data-Pages
• von Neumann-Architecture, which is internally
  equipped with Multi-BUS-Structures to avoid
  BUS-Bottlenecks
• Internal Address Space
• 2 KByte RAM
• 64 KBytes Flash/OTP ROM (One Time Programmable
  ROM)(C164CI-8FM)
• Flexible external BUS-Configurations
• Up to 22-Bit Address-BUS / 8-Bit Data-BUS
  (multiplexed)
• Up to 22-Bit Address -BUS / 16- Bit Data-BUS
  (multiplexed)
• 5 completely independent configuration-registers
• 4 programmable Chip Selects and programmable
  BUS-control signals help to avoid external logic.

9
Internal and external address mapping of the
C164CI
10
The programming language C for the C164

• C166 is the realisation of ANSI-C for the
  microcontroller-family C166.
• The C166-Compiler provides a number of extensions
  of the ANSI-C Standard. Ispecially such, that
  directly support the C 166-architecture

11
The programming language C for the
microcontroller C164

• C166-denotation commentary
• register bank (using) Each function can contain
  a declaration, in which the register bank to be
  used can be set.
• interrupt Functions can declared als
  Interrupt-Service-Routines by indication of the
  interrupt names respectively vectors.
• register mask The C166-Compiler generates for
  each C-function a register-mask, in which the
  registers used by the function are listed. Those
  can be used as funktion prototype, due to
  optimize the usage of the registers.
• RTX166 tasks By the keyword _task_ the functions
  is specified as a task of the operating system
  RTX166.

New Keywords (summarisation) Memory
types near, idata, bdata, sdata, far, huge,
xhuge Data types bit, sfr, sbit Functions interr
upt, _task_, using
12
The programming language C for the
microcontroller C164

• Memory Types
• Type Address space
• near 16-Bit addresses up to 64 kBytes
• idata On-chip RAM (fastest access)
• bdata Bit-addressable On-chip-RAM
• sdata System Page (0xC000-0xFFFF)
  inclusive SFRs
• far 32-Bit Pointer with 16-Bit address
  calculation, the size of the object is 16 kByte.
• huge 32-Bit Pointer with 16-Bit,
  address calculation, the size of the object is
  32 kByte.
• xhuge 32-Bit Pointer with 32-Bit
  address calculation, the size of the object is
  16 MByte.

13
The programming language C for the
microcontroller C164

• According to the memory types memory models can
  be predeterminded as presettings, which always
  will be used, when no memory type is explicitly
  specified by the variable or function
• This is done by the preprocessor directive
  pragma storage model

14
The programming language C for the
microcontroller C164

• Data types size of memory and range of values
• Datentyp size of memory range of values
• bit 1 Bit 0 or 1
• signed char 1 Byte -128 to 127
• unsigned char 1 Byte 0 to 255
• signed int 2 Bytes -32768 to 32767
• unsigned int 2 Bytes 0 to 65535
• signed long 4 Bytes -2147483648 to 2147483642
• unsigned long 4 Bytes 0 to 4294967295
• float 4 Bytes ?1.176E-38 to ?3.40E38
• double 8 Bytes ?1.7E-308 to ?1.7E308
• pointer 2/4 Bytes Address of the object

15
Integrated Development Environment
Start of lab practical
16
Code-addressing using segmentationin the 4 MByte
address space
Code Segment Pointer (CSP) for Code-Addressing
22-Bit physical Code-Addresse (C164)
The Instruction Pointer (IP) is incremented
after each instruction fetch phase The Code
Segment Pointer (CSP) is only changed by
absolute jumps, respectively indirect y in case
of the return from a subroutine by the stack
17
Addressing of data by paging within the 4 MByte
Address space
Data addressing via the Data Page Pointer (DPP)
SFR
18
External Bus Controller

• Allows variable timing of CPU-controlling
  signals by software
• Realizes up to 4 Chip-Select-Signals
• Selection of 4 address ranges possible

Special Function Register BUSCON0..4 Programmable
timings Determinition of CS - signals Selection
of the bandwith of the Data-BUS 8 / 16 Bit
Special Function Register ADDRSEL1..4 Programmable
ranges of the address space for the access to
external components with the properties of the
assigned BUSCONx- registers.
19
Multiplexed Address- and Data-BUS
Extension of the Address-Setups
Memory-Access Time
Tri-State - Time
A16..A21
Address
ALE
CS
A0..A15 D0..D15 (7)
Address
Data
RD
RD-Delay
A0..15 D0..15 (7)
Address
Data
WR
WR-Delay
SFR
20
Integrated Chip Select - Signals
CS0 P6.0 BUSCON0 CS1 P6.1 BUSCON1 ADDRSEL1 CS2
P6.2 BUSCON2 ADDRSEL2 CS3 P6.3 BUSCON3 ADDRSEL3

Active for those address space, which is not
covered by CS1..CS3
The base address is always a multiple of the
address space. (i.e. the Chip Select with an
adress range of 128kByte starts at a 128kByte
boundary)
21
Connection of external memory chips with 8 Bit -
organisation
MT5LC128K8D4
MT5LC128K8D4
MT5LC128K8D4 Fa. Micron SRAM 128k x 8 access
time 25 ns ADDRSEL1 0x0406 BUSCON1 0x04CF
RAM
RAM
A0-16
A0-16
D0-7
WE
WE
C164 20 MHz
OE
OE
CE
D0-7
CE
WRL WRH RD D0-15 A16-19 CS1 CS0ALE
AM27C040 Fa. AMD Eprom 512k x 8 access time 120
ns BUSCON0 0x04CE
D0-7
OE
OE
CS
CS
D0-7
EN
A0-18
A0-18
ROM
ROM
A1-15
15-Bit D-Latch
AM27C040
AM27C040
22
Connection of external memory chipswith 16 Bit-
organisation
IDT71016
IDT71016Co. IDT (Integrated Device
Technology) SRAM 64k x 16 Access time 20
ns ADDRSEL1 0x0405 BUSCON1 0x04CF
RAM
BHE
D0-15
A0-15
BLE
WE
C164 20 MHz
OE
CE
WR BHE RD D0-15 A16-17 CS1 CS0 ALE
M27C202 Co. ST Microelectronics ST Eprom 128k x
16 Access time 100 ns BUSCON0 0x04CE
EN
OE
CS
D0-15
A0-16
A0
A1-15
ROM
16-Bit D-Latch
M27C202
23
Overlapping Address Ranges
24
Interrupt System

• Interrupt Controller
• Short interrupt-reaction timesMin. 250ns,
  typical 400ns (_at_20 MHz)
• Low overhead for ISRs
• Powerful priorisationin 15 priority levels,
  each in 4 groups
• Hardware Traps detects run time error
• Software Traps

• Peripheral Events Controller (PEC)
• Releases the CPU from simple and frequently
  arising ISRs
• Interrupt controlled DMA-simular data transfer
  with CPU-participation
• Reaction times Min. 150ns, typical 300ns with a
  CPU-load of 100ns (_at_20 MHz)

25
Interrupts und PEC - Priorisation
26
Interrupt Processing
if higher priority
Group Check
Priority-Check
Periph. Interrupt
Periph. Interrupt
Comparision of theinterrupt priority with the
run-time-priority of the CPU
Periph. Interrupt
External Interrupt
PEC Service
Periph. Interrupt
16 Priority-Levels
4 Groups
External Interrupt
External Interrupts are possible e.g. instead
of the Capture Inputs
32 Peripheral Interrupts
13 ext. Interrupts ( NMI) including 4 fast
interrupts
Dave
SFR
I-Vektor-Tabelle
µV-v1_isr
Dave v1_isr
27
Peripheral Events Controller (PEC)
Interrupt has passed priority- and group-check
Interrupt Priority 14 or 15 and Data Counter gt 0
Interrupt Priority lt 14
Interrupt Service
PEC Service
Memory Segment 0
0xFFFF
Peripheral Events Contoller
Contr. Reg.
INTR Service Rescuing PSW, CSP, IP New
CPU-Prio. in PSW. CSP and IP
from peripheral-vector or Trap-Number
8 PEC Channels
Data Counter
Byte bzw. Word Transfer
SRC Pointer
DEST Pointer
Prioritäts- GroupCheck
0x0000
Interrupt if Data Counter 0
Demo v1a_isr_pec
SFR