Ciclo 6

1
Ciclo 6
Determinou o endereço de A
A
03 - or r5,r6,r7
06 - add r1,r2,r3
04 - sub r8,r9,r10
02 - and r2,r3,r4
05 - xor r11,r12,r13
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
add r1,r2,r3 Instr. 07 and r2,r3,r4 Instr. 08
or r5,r6,r7 Instr. 09 sub r8,r9,r10 Instr. 10
xor r11,r12,r13
WB Data
Imm
RD
RD
RD
2
Ciclo 7
Determinou o endereço de A
A
07 - and r2,r3,r4
03 - or r5,r6,r7
06 - add r1,r2,r3
05 - xor r11,r12,r13
04 - sub r8,r9,r10
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
add r1,r2,r3 Instr. 07 and r2,r3,r4 Instr. 08
or r5,r6,r7 Instr. 09 sub r8,r9,r10 Instr. 10
xor r11,r12,r13
WB Data
Imm
RD
RD
RD
3
Ciclo 8
Determinou o endereço de A
A
04 - sub r8,r9,r10
08 - or r5,r6,r7
07 - and r2,r3,r4
06 - add r1,r2,r3
05 - xor r11,r12,r13
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
add r1,r2,r3 Instr. 07 and r2,r3,r4 Instr. 08
or r5,r6,r7 Instr. 09 sub r8,r9,r10 Instr. 10
xor r11,r12,r13
WB Data
Imm
RD
RD
RD
4
Ciclo 9
Determinou o endereço de A
A
08 - or r5,r6,r7
07 - and r2,r3,r4
06 - add r1,r2,r3
05 - xor r11,r12,r13
09 - sub r8,r9,r10
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
add r1,r2,r3 Instr. 07 and r2,r3,r4 Instr. 08
or r5,r6,r7 Instr. 09 sub r8,r9,r10 Instr. 10
xor r11,r12,r13
WB Data
Imm
RD
RD
RD
5
Ciclo 10
Determinou o endereço de A
A
08 - or r5,r6,r7
07 - and r2,r3,r4
06 - add r1,r2,r3
09 - sub r8,r9,r10
10 - xor r11,r12,r13
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
add r1,r2,r3 Instr. 07 and r2,r3,r4 Instr. 08
or r5,r6,r7 Instr. 09 sub r8,r9,r10 Instr. 10
xor r11,r12,r13
WB Data
Imm
RD
RD
RD
6
Ciclo 6 Com dependência de dados
Determinou o endereço de A
A
03 - or r5,r6,r7
06 - add r1,r2,r3
04 - sub r8,r9,r10
02 - and r2,r3,r4
05 - xor r11,r12,r13
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
add r1,r2,r3 Instr. 07 and r2,r1,r4 Instr. 08
or r5,r6,r7 Instr. 09 sub r8,r9,r10 Instr. 10
xor r11,r12,r13
WB Data
Imm
RD
RD
RD
7
Ciclo 7
Determinou o endereço de A
A
07 - and r2,r1,r4
03 - or r5,r6,r7
06 - add r1,r2,r3
05 - xor r11,r12,r13
04 - sub r8,r9,r10
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
add r1,r2,r3 Instr. 07 and r2,r1,r4 Instr. 08
or r5,r6,r7 Instr. 09 sub r8,r9,r10 Instr. 10
xor r11,r12,r13
WB Data
Imm
RD
RD
RD
8
Ciclo 8
Determinou o endereço de A
A
04 - sub r8,r9,r10
08 - or r5,r6,r7
07 - and r2,r1,r4
06 - add r1,r2,r3
05 - xor r11,r12,r13
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
add r1,r2,r3 Instr. 07 and r2,r1,r4 Instr. 08
or r5,r6,r7 Instr. 09 sub r8,r9,r10 Instr. 10
xor r11,r12,r13
WB Data
Imm
RD
RD
RD
9
Ciclo 9
Determinou o endereço de A
A
08 - or r5,r6,r7
06 - add r1,r2,r3
05 - xor r11,r12,r13
bolha
07 - and r2,r1,r4
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
add r1,r2,r3 Instr. 07 and r2,r1,r4 Instr. 08
or r5,r6,r7 Instr. 09 sub r8,r9,r10 Instr. 10
xor r11,r12,r13
WB Data
Imm
RD
RD
RD
10
Ciclo 10
Determinou o endereço de A
A
08 - or r5,r6,r7
07 - and r2,r1,r4
06 - add r1,r2,r3
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
add r1,r2,r3 Instr. 07 and r2,r1,r4 Instr. 08
or r5,r6,r7 Instr. 09 sub r8,r9,r10 Instr. 10
xor r11,r12,r13
WB Data
Imm
RD
RD
RD
11
Ciclo 11
Determinou o endereço de A
A
08 - or r5,r6,r7
07 - and r2,r1,r4
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
add r1,r2,r3 Instr. 07 and r2,r1,r4 Instr. 08
or r5,r6,r7 Instr. 09 sub r8,r9,r10 Instr. 10
xor r11,r12,r13
WB Data
Imm
RD
RD
RD
12
Ciclo 12
Determinou o endereço de A
A
08 - or r5,r6,r7
07 - and r2,r1,r4
09 - sub r8,r9,r10
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
add r1,r2,r3 Instr. 07 and r2,r3,r4 Instr. 08
or r5,r6,r7 Instr. 09 sub r8,r9,r10 Instr. 10
xor r11,r12,r13
WB Data
Imm
RD
RD
RD
13
Ciclo 13
Determinou o endereço de A
A
08 - or r5,r6,r7
07 - and r2,r3,r4
09 - sub r8,r9,r10
10 - xor r11,r12,r13
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
add r1,r2,r3 Instr. 07 and r2,r3,r4 Instr. 08
or r5,r6,r7 Instr. 09 sub r8,r9,r10 Instr. 10
xor r11,r12,r13
WB Data
Imm
RD
RD
RD
14
Forwarding
MEM/WR
ID/EX
EX/MEM
NextPC
mux
Registers
Data Memory
mux
mux
Immediate
15
Ciclo 6 Com forwarding
Determinou o endereço de A
A
03 - or r5,r6,r7
06 - add r1,r2,r3
04 - sub r8,r9,r10
02 - and r2,r3,r4
05 - xor r11,r12,r13
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
add r1,r2,r3 Instr. 07 and r2,r1,r4 Instr. 08
or r5,r1,r7 Instr. 09 sub r8,r1,r10 Instr. 10
xor r11,r1,r13
WB Data
Imm
RD
RD
RD
16
Ciclo 7
Determinou o endereço de A
A
07 - and r2,r1,r4
03 - or r5,r6,r7
06 - add r1,r2,r3
05 - xor r11,r12,r13
04 - sub r8,r9,r10
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
add r1,r2,r3 Instr. 07 and r2,r1,r4 Instr. 08
or r5,r1,r7 Instr. 09 sub r8,r1,r10 Instr. 10
xor r11,r1,r13
WB Data
Imm
RD
RD
RD
17
Ciclo 8
Vai ler o valor errado no fim do ciclo
Determinou o endereço de A
A
04 - sub r8,r9,r10
08 - or r5,r1,r7
07 - and r2,r1,r4
06 - add r1,r2,r3
05 - xor r11,r12,r13
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
add r1,r2,r3 Instr. 07 and r2,r1,r4 Instr. 08
or r5,r1,r7 Instr. 09 sub r8,r1,r10 Instr. 10
xor r11,r1,r13
WB Data
Imm
RD
RD
RD
18
Ciclo 9
Vai ler o valor errado no fim do ciclo
Usa o valor correto via forwarding
Determinou o endereço de A
A
08 - or r5,r1,r7
07 - and r2,r1,r4
06 - add r1,r2,r3
05 - xor r11,r12,r13
09 - sub r8,r1,r10
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
add r1,r2,r3 Instr. 07 and r2,r1,r4 Instr. 08
or r5,r1,r7 Instr. 09 sub r8,r1,r10 Instr. 10
xor r11,r1,r13
WB Data
Imm
RD
RD
RD
19
Ciclo 10
Vai ler o valor certo no fim do ciclo
Usa o valor correto via forwarding
Determinou o endereço de A
A
08 - or r5,r1,r7
07 - and r2,r1,r4
06 - add r1,r2,r3
09 - sub r8,r1,r10
10 - xor r11,r1,r13
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
add r1,r2,r3 Instr. 07 and r2,r1,r4 Instr. 08
or r5,r1,r7 Instr. 09 sub r8,r1,r10 Instr. 10
xor r11,r1,r13
WB Data
Imm
RD
RD
RD
Registradores feitos com FFs tipo D acionados por
nível
20
Ciclo 8 Dependência verdadeira - LW
Determinou o endereço de A
A
04 - sub r8,r9,r10
08 - or r5,r6,r7
07 - and r2,r1,r4
06 - lw r1,0(r3)
05 - xor r11,r12,r13
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
lw r1,0(r3) Instr. 07 and r2,r1,r4 Instr. 08
or r5,r6,r7 Instr. 09 sub r8,r9,r10 Instr. 10
xor r11,r12,r13
WB Data
Imm
RD
RD
RD
21
Ciclo 9
Determinou o endereço de A
A
08 - or r5,r6,r7
07 - and r2,r1,r4
06 - lw r1,0(r3)
05 - xor r11,r12,r13
bolha
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
lw r1,0(r3) Instr. 07 and r2,r1,r4 Instr. 08
or r5,r6,r7 Instr. 09 sub r8,r9,r10 Instr. 10
xor r11,r12,r13
WB Data
Imm
RD
RD
RD
22
Ciclo 10
Determinou o endereço de A
A
08 - or r5,r6,r7
06 - lw r1,0(r3)
bolha
09 - sub r8,r1,r10
07 - and r2,r1,r4
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
lw r1,0(r3) Instr. 07 and r2,r1,r4 Instr. 08
or r5,r6,r7 Instr. 09 sub r8,r9,r10 Instr. 10
xor r11,r12,r13
WB Data
Imm
RD
RD
RD
23
Ciclo 6 Desvios condicionais bolhas
para trás
Determinou o endereço de A
A
03 - or r5,r6,r7
06 - beqz r1, i10
04 - sub r8,r9,r10
02 - and r2,r3,r4
05 - xor r11,r12,r13
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
beqz r1, i10 Instr. 07 and r2,r3,r4 Instr. 08
or r5,r6,r7 Instr. 09 sub r8,r9,r10 Instr. 10
xor r11,r12,r13
WB Data
Imm
RD
RD
RD
24
Ciclo 7
Determinou o endereço de A
A
07 - and r2,r3,r4
03 - or r5,r6,r7
05 - xor r11,r12,r13
04 - sub r8,r9,r10
06 - beqz r1, i10
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
beqz r1, i10 Instr. 07 and r2,r3,r4 Instr. 08
or r5,r6,r7 Instr. 09 sub r8,r9,r10 Instr. 10
xor r11,r12,r13
WB Data
Imm
RD
RD
RD
25
Ciclo 8
Determinou o endereço de A
A
04 - sub r8,r9,r10
08 - or r5,r6,r7
07 - and r2,r3,r4
05 - xor r11,r12,r13
06 - beqz r1, i10
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
beqz r1, i10 Instr. 07 and r2,r3,r4 Instr. 08
or r5,r6,r7 Instr. 09 sub r8,r9,r10 Instr. 10
xor r11,r12,r13
WB Data
Imm
RD
RD
RD
26
Ciclo 9
Determinou o endereço de A
A
08 - or r5,r6,r7
anulada
anulada
07 - and r2,r3,r4
05 - xor r11,r12,r13
06 - beqz r1, i10
10 - xor r11,r12,r13
Next PC
MUX
Next SEQ PC
Next SEQ PC
Zero?
RS1
Reg File
MUX
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
Instr. 01 add r1,r2,r3 Instr. 02 and
r2,r3,r4 Instr. 03 or r5,r6,r7 Instr. 04 sub
r8,r9,r10 Instr. 05 xor r11,r12,r13 Instr. 06
beqz r1, i10 Instr. 07 and r2,r3,r4 Instr. 08
or r5,r6,r7 Instr. 09 sub r8,r9,r10 Instr. 10
xor r11,r12,r13
WB Data
Imm
RD
RD
RD
27
Pipeline melhorado
Memory Access
Instruction Fetch
Execute Addr. Calc
Write Back
Instr. Decode Reg. Fetch
Next SEQ PC
Next PC
MUX
Adder
Zero?
RS1
Reg File
Memory
RS2
Data Memory
MUX
MUX
Sign Extend
WB Data
Imm
RD
RD
RD

• Perda de apenas um ciclo se o desvio for tomado

28
Four Branch Hazard Alternatives

• 1 Stall until branch direction is clear
• 2 Predict Branch Not Taken
• Execute successor instructions in sequence
• Squash instructions in pipeline if branch
  actually taken
• Advantage of late pipeline state update
• 47 MIPS branches not taken on average
• PC4 already calculated, so use it to get next
  instruction
• 3 Predict Branch Taken
• 53 MIPS branches taken on average
• But havent calculated branch target address in
  MIPS
• MIPS still incurs 1 cycle branch penalty
• Other machines branch target known before outcome

29
Four Branch Hazard Alternatives

• 4 Delayed Branch
• Define branch to take place AFTER a following
  instruction
• branch instruction sequential
  successor1 sequential successor2 ........ seque
  ntial successorn
• branch target if taken
• 1 slot delay allows proper decision and branch
  target address in 5 stage pipeline
• MIPS uses this

Branch delay of length n
30
Escalonando Branch Delay Slots
A. From before branch
B. From branch target
C. From fall through
add 1,2,3 if 10 then
add 1,2,3 if 20 then
sub 4,5,6
delay slot
delay slot
add 1,2,3 if 10 then
sub 4,5,6
delay slot

• A é a melhor escolha, pois enche o slot e reduz a
  contagem de instruções (CI)
• Em B, a instrução sub pode precisar ser copiada,
  aumentando a CI
• Em B e C, não pode haver problemas em executar a
  sub quando o desvio não é tomado

31
Delayed Branch

• Compiler effectiveness for single branch delay
  slot
• Fills about 60 of branch delay slots
• About 80 of instructions executed in branch
  delay slots useful in computation
• About 50 (60 x 80) of slots usefully filled
• Delayed Branch downside As processor go to
  deeper pipelines and multiple issue, the branch
  delay grows and need more than one delay slot
• Delayed branching has lost popularity compared to
  more expensive but more flexible dynamic
  approaches
• Growth in available transistors has made dynamic
  approaches relatively cheaper

32
Evaluating Branch Alternatives

• Assume 4 unconditional branch, 6 conditional
  branch- untaken, 10 conditional branch-taken
• Scheduling Branch CPI speedup v. speedup v.
  scheme penalty unpipelined stall
• Stall pipeline 3 1.60 3.1 1.0
• Predict taken 1 1.20 4.2 1.33
• Predict not taken 1 1.14 4.4 1.40
• Delayed branch 0.5 1.10 4.5 1.45

33
Problems with Pipelining

• Exception An unusual event happens to an
  instruction during its execution
• Examples divide by zero, undefined opcode
• Interrupt Hardware signal to switch the
  processor to a new instruction stream
• Example a sound card interrupts when it needs
  more audio output samples (an audio click
  happens if it is left waiting)
• Problem It must appear that the exception or
  interrupt must appear between 2 instructions (Ii
  and Ii1)
• The effect of all instructions up to and
  including Ii is totalling complete
• No effect of any instruction after Ii can take
  place
• The interrupt (exception) handler either aborts
  program or restarts at instruction Ii1

34
Precise Exceptions in Static Pipelines
Key observation architected state only change in
memory and register write stages.
35
Outra alternativa para reduzir o impacto dos
desvios condicionais

• Predição de desvios!
• Mas, para compreender como implementar,
  precisamos saber como funcionam os caches!