EDUSAT SESSION FOR

1
EDUSAT SESSION FOR ADVANCED MICROPROCESSOR
(EC54) Date 09.12.2005 Session VIII Topic PCI
BUS Faculty Anita Kanavalli MSRIT
2
I/O Device

CPU
Main Memory
BUS (PCI, ISA, etc.)
cable
Device Controller
I/O
Low-level device interface (SCSI, IDE, etc.)
3
I/O Device

• Consists of
• A mechanical part device itself
• An electronic part the device controller
• Printed circuit card that is plugged in to the
  slot of a computer.

4
BUS

• A bus is used to communicate between components
  in a computer system.
• An important distinction to be drawn early is
  that between a bus and a point-to-point network.
• A bus has a single wire, or connection of wires
  with multiple sources and destinations.
• A point-to-point network has some sort of
  interconnection scheme between sources and
  destinations in which the nodes are endpoints.

5
BUS

• Bus operations should be thought of in terms of
  transactions.
• A bus transaction is an operation on the bus
  for instance, a memory read, or an interrupt
  service, or an IO write.
• A bus transaction is initiated by a bus master
  who requests that some operation take place a
  slave will respond to the transaction
  appropriately.
• Different busses support different sets of
  transactions.

6
Data Transfer

CPU
Main Memory

Address lines
Data lines
read line
Bus
write line
Memory/IO
I/O device controller
I/O device controller
I/O device controller
7
Data Transfer Separate I/O Space

• Assume we will do a read!
• CPU puts the address on the bus
• CPU activates the read line
• CPU asserts a signal line that says whether we
  will read from memory or I/O device

8
Data Transfer Separate I/O Space

• If we will read from memory
• Address lines contains a memory address from the
  memory address space
• Main Memory responds.
• If we will read from I/O device
• Address lines contain an address from I/O port
  address space.
• Respective device controller responds

9
Data Transfer Memory mapped I/O

• Assume we will do a read!
• CPU puts the address on the bus
• CPU activates the read line
• If we will read from memory
• Address lines contain an address from part of
  address space for main memory
• Main Memory responds.

10
Data Transfer Memory mapped I/O

• If we will read from I/O device
• Address lines contain an address from part of
  address space for device controllers.
• Respective device controller responds

11
PCI BUS

• The Peripheral Component Interconnect (PCI) bus
  is the standard I/O bus on recent computers in
  general, and PCs in particular.
• It was developed by Intel in 1993 to replace the
  various busses which had been in use on both PCs
  and Macintoshes.
• It is a 32-bit, 33MHz bus with multiplexed
  address and data, and very nice capabilities for
  autoconfiguration ("Plug and Play"). It also
  supports both old, 5 volt devices and newer, 3.3
  volt devices.

12
PCI BUS

• All transfers on the PCI bus are "burst"
  transfers. What this means is that once a device
  obtains the bus to perform a transfer, it is able
  to hang on to the bus indefinitely, and keep
  sending more data every bus cycle (there's
  actually a timer in the bus controller which will
  take control back after some configurable time
  period, to keep transfers from being too long.
  The longer the transfers are the better the
  throughput, but this can cause unacceptable
  delays for other devices).

13
PCI Address/Data Connections

• The address and data bus ADO-AD31
• During the first clocking period the address or
  I/O location appears on AD lines.
• Command to the peripheral appears on the C/BE
  pins
• There are 16 PCI bus commands

14
PCI Address/Data Connections

Command Command Type 0000
Interrupt Acknowledge 0001
Special Cycle 0010
I/O Read 0011 I/O
Write 0100 reserved 0101
reserved
15
PCI Address/Data Connections

0110 Memory Read 0111
Memory Write 1000
reserved 1001
reserved 1010 Configuration
Read
16
PCI Address/Data Connections

• 1011 Configuration Write
• 1100 Multiple Memory Read
• 1101 Dual Address Cycle
• 1110 Memory-Read Line
• 1111 Memory Write and
  Invalidate

17
PCI Address/Data Connections

Interrupt Acknowledge (0000) The interrupt
controller automatically recognizes and reacts to
the INTA (interrupt acknowledge) command. In the
data phase, it transfers the interrupt vector to
the AD lines.
18
PCI Address/Data Connections

• Special Cycle (0001)
• AD15-AD0
• 0x0000 Processor Shutdown
• 0x0001 Processor Halt
• 0x0002 x86 Specific Code
• 0x0003 to 0xFFFF Reserved

19
PCI Address/Data Connections

• I/O Read (0010) and I/O Write (0011)
• Input/Output device read or write operation. The
  AD lines contain a byte address (AD0 and AD1 must
  be decoded). PCI I/O ports may be 8 or 16 bits.
  PCI allows 32 bits of address space.
• The PCI configuration space may also be accessed
  through I/O ports 0x0CF8 (Address) and 0x0CFC
  (Data). The address port must be written first.

20
PCI Address/Data Connections

• Configuration Read (1010) and Configuration
  Write (1011)
• A read or write to the PCI device configuration
  space, which is 256 bytes in length. It is
  accessed in doubleword units. AD0 and AD1 contain
  0, AD2-7 contain the doubleword address, AD8-10
  are used for selecting the addressed unit a the
  malfunction unit, and the remaining AD lines are
  not used.

21
PCI Address/Data Connections

• Memory-Read Line (1110)
• This cycle is used to read in more than two 32
  bit data blocks, typically up to the end of a
  cache line. It is more effecient than normal
  memory read bursts for a long series of
  sequential memory accesses.

22
CONFIGURATION SPACE

23
Configuration Space

• One of the nicest features of PCI is its support
  for autoconfiguration.
• In addition to every device having an address on
  the PCI bus, every card has its own address
  determined by which slot it is plugged into. This
  is referred to as the card's configuration space,
  and can be queried (and parts of it can be
  written) by the CPU.
• This normally occurs at boot time it may be
  performed by the BIOS prior to starting the boot
  loader, or it may be performed by the OS as it
  boots.

24
Configuration Space

• The first 64 bytes of the configuration space
  the header holds information about the interface.
• The first 32 bit doubleword contain the unit ID
  code.
• Each of the other bytes have different
  information.
• The second double word is the Status/Command
  control information.

25
Interrupt Handling

• PCI uses four pins, called INTA-INTD, for
  interrupt requests.
• When an interrupt is required, the proper pin is
  asserted.
• A card which only has a single interrupt will
  normally use INTA
• In the modern systems BIOS exists which support
  PCI bus

26
Questions

1 With respect to the PCI bus discuss the
following configuration space Plug and
play Bus commands 2 Write a note on interrupt
handling in PCI bus 3 What are features of the
PCI bus and why is it superior compared to other
type of bus.