Jeff Allen

1
ECE 572/672 Project Testing

• Jeff Allen
• Jacob Biamonte

2
Other important moments in the history of quantum
test set generation

• Original Idea from right here at PSU!
• Markov/Hayes at the U.M. ? work was done on
  reversible test set generation that at least made
  one think about quantum test set generation (We
  are the only group in the world to cite this
  paper thus far) This is one of the most
  fundamental papers published in recent times!
• Many papers exist on regular testing, U.M. group
  and us are the only ones doing this research now
  (I think anyway), when reversible computers
  become commercial 1,000s of test set generation
  papers will be written, we just dont know when
  this will happen but we hope it will be in our
  life times.
• Ed Perkins wrote some reversible test generation
  software last year, he did a good job but I have
  a new method and new software

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Goal Number One

• Illustrate classical known method to detect and
  localize faults on a simple AND gate
• Explain the classical fault model
• Explain the use of this in large scale binary and
  analog circuit design

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Classical Fault Localization

• Example 1 AND gate inserting stuck-at faults.

Good Circuit

• Seven possible situations

Stuck-at-1 at a
Stuck-at-1 at b
Stuck-at-1 at y
Sa1
Sa1
Sa1
Stuck-at-0 at a
Stuck-at-0 at y
Stuck-at-0 at b
Sa0
Sa0
Sa0
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Classical Fault Localization

• Create truth table showing good circuit and all
  cases of faults

? Indicates a faulty output (output different
than that of good circuit)

• Goal minimize the number of test vectors needed
  to detect and localize all faults

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Classical Fault Localization
Input Vectors Chosen so as to detect and localize
all faults with minimum number of test vectors
b
sa0 y
sa0
sa0 a
sa1 y
sa1 b
sa1 a
Good Circuit
a
T1
0
X
0
T2
1
X
X
0
T3
0
X
X
1
T4
1
X
X
X
1
Fault Table of AND gate with stuck at faults
Before Test
Possible Good Circuit, sa1 a, sa1 b, sa1 y, sa0
a, sa0 b, sa0 y
Applying Test Vector 01
After Test
Possible sa1 a, sa1 y
Possible Good Circuit, sa1 b, sa0 a, sa0 b, sa0 y
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b
sa0 y
sa0
sa0 a
sa1 y
sa1 b
sa1 a
Good Circuit
a
Original Fault Table
T1
0
X
0
T2
1
X
X
0
T3
0
X
X
1
Good Circuit, sa1 a, sa1 b, sa1 y, sa0 a, sa0 b,
sa0 y
T4
1
X
X
X
1
Good Circuit, sa1 b, sa0 a, sa0 b, sa0 y
sa1 a, sa1 y
Good Circuit, sa0 a, sa0 b, sa0 y
Because all of the stuck-at-0 faults have the
same entries in the fault table, there is no way
to localize them, unless we can measure all parts
of the circuit.
If we would have tested exhaustively it would
have taken all 4 tests, we did it in 3, (and we
know the type of error present!)
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Goal Number Two

• Show another example, but this time with a
  reversible circuit and Markov, Hayes stuck-at
  technique
• Explain some of the differences between classical
  fault detection and reversible fault detection

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Example 2, a reversible circuit
?

• Stuck-at-0

?
?
Stuck-at-1
?
?
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Example 2 continued
Locations for faults
?
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Example 2 continued
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Example 2 B, localization
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Example 2 B, localization
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Compare Scaling Reversible v. Classical

• Small reversible circuits have small gains
  compared to classical
• Large Classical circuits often cannot be
  localized, where all reversible circuits can be
  localized

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Reversible scaling

• Each level of a reversible circuit can be
  partially tested with any test
• A first test will test every C-NOT gates input,
  output and control half way

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Example 2 revisited
Locations for faults
?
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Reversible scaling (cont)

• The best each subsequent test can do is half of
  what is left.
• Test overlap exists and can lower each successive
  tests effectiveness

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My Approach

• Path propagation as opposed to fault tables
• The Stuck-at model is incomplete
• What about missing gate?
• Bridging faults

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Whats wrong with fault tables?

• Memory requirements, a non linear increase exists
  when lines, stages, and or gates are added.
• Good tables may require conditional branch
  solutions for localization.

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Why Path Propagation?

• Dynamic on the fly localization
• Circuit can be loaded and testing can be started
  immediately.
• Can be optimized to find known issues
• Capable of providing OTF coverage specs

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Path Propagation Example (Step One)
1 1 0
1 1 1
S0
s0 s0 S1
S0
S0
s1 !s0 S0
S0 S1
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Path Propagation Example (Step Two)
1 1 0
0 1 1
0
S1
S0
S0
S1
S0
s1 s0 S0
s0 s0 S0
s1 ! S0
s0 s0 S1
S0 S1
S1 S0
1
0
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Path Propagation Example (Step Three)
0
0


s1 S1
s1
S0
s0 S0
s1 S0
s0
S1

0
0
1
1
Note Y-Stuck at 0 stage 1 never tested. And Stuck
_at_ 0 can be missed in case of missing gates
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Our Test Set

• 110
• 011
• 001
• 10 to test Y-stuck_at_0 stage 1

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What does this mean?

• The stuck at method can miss errors involving
  missing gates
• 50 likely to miss, missing gate in stage 1
• Law of diminishing returns, how does it apply
  here?

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Bridging Faults

• In order to truly test bridging across lines
  one-hot and one-cool versions should be done
• If single fault model used, implied bridging
  could be attempted

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Implied Bridging Technique

• At each connection and or xor two lists of all
  other lines for 1-0 and 0-1 oppositions
• Percent bridge tested equals
• ((tested 1-0) (tested 0-1)) / (2 totalnodes)

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Thanks!

• As can be seen by the example there are more
  calculations then what can be done by hand for
  larger circuits
• Typically there is redundancy in the exhaustive
  method, this is far to complicated to be seen for
  people, but computers can remove it. The goal of
  this method is to remove the useless tests, and
  focus on the tests that give the most information
  about the circuit.