LCLS Timing - PowerPoint PPT Presentation

About This Presentation
Title:

LCLS Timing

Description:

System requirements (speed and content) are known: receive 128 bit PNET data at ... Driver and device support (bi, mbbiDirect to access each variable in ... – PowerPoint PPT presentation

Number of Views:38
Avg rating:3.0/5.0
Slides: 13
Provided by: DayleK4
Category:
Tags: lcls | content | timing

less

Transcript and Presenter's Notes

Title: LCLS Timing


1
LCLS Timing
  • Outline
  • Scope
  • The order of things
  • Introducing the PNET VME receiver
  • Status of the PNET VME receiver
  • System diagram
  • Looking at timing pulse to pulse
  • LCLS MPG
  • EVG
  • Conclusions

2
Scope
  • LCLS timing system is used to transmit a fiducial
    360 Hz signal to all triggered devices in LCLS
  • System requirements (speed and content) are
    known receive 128 bit PNET data at 360 Hz
    append addl info operate at 120 Hz
  • The component parts are known PNET VME receiver,
    EVG-200 and EVR-200
  • The interfaces are being defined

3
The order of things
  • The one and only SLC Master Pattern Generator
    (MPG)
  • Takes as input 360 Hz fiducial from SLC PDU is
    the signal to create a new PNET buffer
  • Performs tasks
  • creates PNET buffers
  • responds to faults
  • Outputs PNET buffers to all micros and PNET VME
    receiver on the next 1/360 s fiducial

4
Introducing the PNET VME receiver
  • N

5
Status of the VME PNET receiver
  • Hardware prototype is finished (1 instance)
  • Board is 3 slots wide to accommodate on board
    cable modem interface to PNET
  • Engineering Design Specification doc written
  • Driver and device support (bi, mbbiDirect to
    access each variable in PNETbuffer) written.
    Compiled only for Synergy PPC running RTEMS 4.6.2

6
System Diagram
7
Looking at timing pulse to pulse
8
Looking at timing pulse to pulse
9
Looking at timing pulse to pulse
10
LCLS MPG
  • Takes the PNETbuffer with appended epicsTimeStamp
    and checksum fault indicators
  • Adds on LCLS application commands
  • Adds on any newly detected faults
  • Informs EVG that data is ready

11
EVG
  • On board FPGA packages/chunks 24 byte LCLS MPG
    data and sends to EVR at 125 MHz
  • Data arrives in EVR in 0.6 microseconds fiber
    travel time (which depends on distance)

12
Conclusions
  • LCLS MPG needs to be designed
  • LCLS MPG/EVG interface needs defining
  • EVR/SLC-aware IOC interface needs defining
  • Performance and reliability from PNET through to
    EVG must be measured
  • But I guess there has been some progress
Write a Comment
User Comments (0)
About PowerShow.com