Title: From problem description to circuit
1Lecture 4
- From problem description to circuit
2In this lecture we will
- Create circuits from Truth Tables.
- Use Karnaugh Maps to minimise circuits.
- Work through a design exercise.
3Analysing and transforming circuits
- So far we have analysed and transformed Digital
circuits - Given a circuit - find its Truth Table.
- Given a Boolean Expression - make it simpler.
4Circuit SYNTHESIS
- The more interesting problem is Synthesis.
- From a given description of the required
behaviour of a circuit (its truth table) design
an actual circuit that implements it. - The solution is NOT unique.
- We will look for Best solution (need to define
Best).
5Two methods which always work
- 1) Synthesise the circuit from the truth table by
using minterms. - ie OR-ing the 1s in the truth table.
- 2) Synthesise the circuit from the truth table by
using maxterms. - ie AND-ing the 0s in the truth table.
6Synthesise a circuit by Minterms
- Given the circuit
- We look at the 1s
0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1
1 0 1 1 1
0
1
0
1
0
1
R
(AB)
(AB)
C
1
1
R
A'B'C
A'BC
AB'C
ABC'
ABC
7Synthesise a circuit by Maxterms
- Given the circuit
- Looking at the 0s
R (ABC)(ABC)(ABC)
8SYNTHESIS The universal hardware solution
0 0 0 ABC
Another 5 stages
The Programmable Array Logic ( PAL)
R
9Programmable Array Logic (PAL) chips
- Programming Antifuse fusable links.
- All possible minterms are considered and added in
the final OR gate. (Only the connected ones are
implemented). - PAL cannot express the Dual - Boolean product of
Maxterms. - BUT Complexity of circuit.
- No benefits in combinatorial minimisation.
10Karnaugh Maps for minimisation
Rearranging the Truth Table of our circuit
C
AB
Minimising on 1s
Minimal circuit
not obvious
Original circuit!
11Karnaugh Maps for minimisation
Now try minimising on 0s (there are fewer of
them!)
R
(BC)
(AC)
Giving the circuit
Again compare with the original circuit!
12Design Exercise - Definition
- Definition of the Problem
- Build a combinatorial digital circuit with three
inputs and one output. - Inputs A and B are data, C is for control
When C 0 Output R A B C 1 R
A B
Design the circuit using two-input AND,
two-input NAND and Inverter gates only.
13Design Exercise - Functional Specification
- The functional specification is thus
R(C0)A B R(C1)A B
14Design Exercise
- Step 1/ Generate the Truth Table
0 00
0 0 0 1
0 01
0 10
0 11
1 00
0 1 1 1
1 01
1 10
1 11
15Design Exercise
- Step 2/ Generate the Karnaugh Map
We can simplify the 4 term canonical expression
either using Boolean Algebra or Karnaugh Maps -
which tends to be easier.
0 1
0 1
0 0
1 1
0 1
Remember the terms on the top line are in the
order 00, 01, 11, 10!
16Design Exercise
- Step 3a/ Minimise the Karnaugh Map
By 1s
R
A B
B C
A C
now factorise
A (B C) B C
or R C (A B) A B
17Design Exercise
- 3b/ Minimise the Karnaugh Map
By 0s
R
(A B)
(A C)
(B C)
(A (B C)) (B C)
or (C (A B)) (A B)
18Design Exercise
- 4/ Build the circuit Minimised by 1s
Expression is-
R A (B C) B C
Corresponding Circuit is-
19The Three Allowed IC Devices
- SN7400 type Integrated circuits
In other words we have 2-input NANDs, 2-input
ANDs, 1-input NOTs.
20Design Exercise
- 5/ Transform Gates into those allowed
NOT
NAND
NAND
NAND
NAND
Insert pairs of NOT gates
Group to form NAND Gates
21Design Exercise
Cost Socket Cost Gate cost 0.5 0.48U
where UUtilisation
NANDs
NOTs
Cost 0.5 (4/4)0.48 0.5 (2/6)0.48
1.64
22Design Exercise
- 7/ Search for cheapest circuit
Going back to original expression BEFORE we
factorised to remove a term.
R AB BC AC
R ((AB) (BC) (AC))
Actually cheaper if allowed to use 3-input NAND
gates.
23Laws of Boolean Algebra
A 0 0 A 1 A
A A A A A A
A B B A A B B A
Commutative laws
Idempotent laws
(AB)C A(BC) (AB)C A(BC)
ABAC A(BC) (AB) (AC) A(BC)
Associative laws
Distributive laws
24Postulates involving NOT
(A) A
involution law
complementary laws
(A B) A B (A B) A B
Dualisation laws or De Morgans theorem