Lexical Conventions in Verilog HDL. (1)

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Verilog HDL Lexical Conventions

• CEC

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Contents

• Operators.
• Number Specifications.
• Identifiers and Keywords.
• Special Characters.
• Data Types, Strings and Arrays.
• System Tasks and Compiler Directives.
• Ports.

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Tokens

• Verilog contains tokens.
• Can be comments, delimiters, numbers, strings,
  identifiers and keywords.
• Case Sensitive - all keywords in lower case.

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Operators

• Unary operators precede the operand.
• Binary operators appear between two operands.
• Ternary operators have two separate operators
  that separate three operands.

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White Space

• Blank spaces (\b), tabs (\t), newlines (\n).
• Normally ignored by Verilog.
• Not ignored in strings.
• Not ignored when it separates tokens.

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Number Specifications

• Sized and unsized numbers.
• Sized numbers specified as
• ltsizegt ltbase formatgt ltnumbergt
• Legal base formats are decimal, hexadecimal,
  binary and octal.

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Number Specifications

• Unsized numbers specified without a base format.
• Default number of bits is machine or simulator
  specific (at least 32 bits).

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Number Specifications

• Negative numbers minus sign before the size of
  a constant number.
• Underscore allowed anywhere except the first
  number.

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Number Specifications

• Unknown number denoted by x.
• High impedance number denoted by z.
• ? as alternative for z.

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Strings

• Treated as a sequence of one-byte ASCII values.
• Enclosed in double quotes.
• Contained on a single line, no carriage return.

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Identifiers and Keywords

• Keywords are special identifiers to define
  language constructs.
• Lower case, identifiers are case sensitive.
• Alphanumeric characters, dollar sign, underscore.
• Escaped identifiers begin with \, end with white
  space.

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Special Characters
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Data Types

• Integer, Real and Time Register Data types.
• Integer general purpose register data type for
  manipulating quantities.

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Data Types

• Real
• specified in decimal or scientific notation.
• - default value is 0.
• - cannot have range declaration.

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Data Types

• Time
• - Verilog simulation done with respect to
  simulation time, measured in simulation seconds.
• - Time register data type used to store
  simulation time.
• - time to get current simulation time.

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Arrays

• Allowed for reg, integer, time and vector
  register data types.
• Accessed by ltarray namegt, ltsubscriptgt.

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Memories

• Memories modelled as array of registers.
• Each element of the array is called word.

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Strings

• Stored in reg, each character takes up 8 bits.
• Truncates leftmost bits of the string if register
  width smaller than string width.

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System Tasks

• Appear in the form of ltkeywordgt.
• display displaying values of variables or
  strings or expressions, inserts a new line at the
  end of the string by default.
• display without argument produces a new line.

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System Tasks
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System Tasks
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System Tasks

• monitor to monitor a signal when its value
  changes.
• Need to be invoked once.
• If more than one monitor statement, the last
  monitor statement will be the active statement.
• monitoron enable monitoring.
• monitoroff disable monitoring.

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System Tasks
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System Tasks

• stop to stop during (suspend) simulation.
• finish - to terminate simulation.

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String Formats
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Compiler Directives

• define to define text macros in Verilog.

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Compiler Directives

• include include a Verilog file into another
  Verilog file.

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Components of a Verilog Module
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Ports

• Interface by which a module interacts with
  external world.
• Input, Output ports.
• Top no list of ports.
• module Top means top level module.

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Ports
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Port Connection/Declaration Rules
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Thank You