FPGA Notes

1
FPGA Notes

• Anselmo Lastra

2
Topics

• A few FPGA tips from Xilinx
• Timing Constraints
• Using Chipscope

3
Timing Constraints

• Period constraint
• Pad-to-Pad
• Offset

4
Period Constraint

• Does not constrain the In and Out paths

FF1
FF2
Combinational Logic
In
Out
Constrains these paths
5
Pad-to-Pad

• Constrains purely combinational logic
• Rare in FPGAs

Combinational Logic
In
Out
6
Offset

• Constrains the in-gtregister and register-gtout
  times
• Probably better to latch inputs and outputs w/o
  logic

FF1
In
Combinational Logic
Constrains these paths
7
Example -- Period
8
Result
Asterisk () preceding a constraint indicates it
was not met. This may be due to a setup or hold
violation. ---------------------------------------
-----------------------------------------
Constraint
Requested Actual
Logic
------------------------------------------------
-------------------------------- TS_clk
PERIOD TIMEGRP "clk" 3 nS HIG 3.000ns
2.876ns 0 H 50.000000
-------------------------------------
------------------------------------------- All
constraints were met. Generating Pad Report.

• That worked. Lets try 2.5ns

9
Constraint Failed
WARNINGPar62 - Timing constraints have not been
met. Asterisk () preceding a constraint
indicates it was not met. This may be due to a
setup or hold violation. -------------------------
--------------------------------------------------
----- Constraint
Requested Actual
Logic --------------------------------------
------------------------------------------
TS_clk PERIOD TIMEGRP "clk" 2.500 nS
2.500ns 2.885ns 0 HIGH 50.000000
------------------------------------------------
-------------------------------- 1 constraint not
met. Generating Pad Report.

• Lets raise Effort Level

10
Properties

• Right-Click Implement Design
• PR Tab
• Effort to High
• Takes more time

11
Made It
Asterisk () preceding a constraint indicates it
was not met. This may be due to a setup or
hold violation. ----------------------------------
----------------------------------------------
Constraint
Requested Actual
Logic --------------------------------------------
------------------------------------ TS_clk
PERIOD TIMEGRP "clk" 2.500 nS 2.500ns
2.439ns 0 HIGH 50.000000
-------------------------------------------------
------------------------------- All constraints
were met. Generating Pad Report.

• This is pushing the chip.
• Design next slide

12
Why It Went So Fast

• The design is very simple
• module basic(clk, idata, odata)
• input clk
• input 70 idata
• output 70 odata
• reg 70 in
• reg 70 odata
• always _at_ (posedge clk)
• begin
• in lt idata
• odata lt in
• end
• endmodule

13
Timing Reports

• Post Map and Post Place Route
• Also a timing estimate is on synthesis report

14
Constraints Met

• Will say
• All constraints were met.
• and display some info about maximum frequency
• Minimum period 15.415ns (Maximum frequency
  64.872MHz)

15
Failed

• Prints failing nets (default top 3 printed)
• Slack -5.415ns (requirement - (data path -
  clock skew))
• Source pic1/instmem_m/instreg_7
  (FF)
• Destination pic1/statreg_m/Z (FF)
• Requirement 10.000ns
• Data Path Delay 15.415ns (Levels of Logic
  13)

16
Detailed Info

• Data Path pic1/instmem_m/instreg_7 to
  pic1/statreg_m/Z
• Location Delay type
  Delay(ns) Physical Resource
• 
  Logical Resource(s)
• ----------------------------------------------
  --- -------------------
• SLICE.XQ Tcko
  0.886 pic1/instlt7gt
• 
  pic1/instmem_m/instreg_7
• SLICE.G1 net (fanout11) e
  0.631 pic1/instlt7gt
• SLICE.Y Tilo
  0.418 pic1/instmem_m_instreglt7gt_1
• 
  pic1/instmem_m_instreglt7gt_1
• SLICE.F2 net (fanout15) e
  0.631 pic1/instmem_m_instreglt7gt_1
• SLICE.X Tilo
  0.418 pic1/alu_m/N33820
• 
  pic1/alu_m/Mmux_Aval_I5_Result35_SW0
• SLICE.F4 net (fanout1) e
  0.631 pic1/alu_m/N33820
• SLICE.X Tilo
  0.418 pic1/alu_m/Mmux_Aval_I5_Result35/O
• 
  pic1/alu_m/Mmux_Aval_I5_Result35
• SLICE.G2 net (fanout2) e
  0.631 pic1/aluZ
• SLICE.CLK Tick
  0.932 pic1/statreg_m/Z
• 
  pic1/statreg_m/Mmux__n0007_Result1

60/40 rule
17
What To Do

• Duplicate FFs
• More pipelining
• Manually place
• Ive never done it
• Can set preferences to display more than 3 signal
  paths

18
Offset Pad to Setup
19
Offset Clock to Pad
20
Pad to Pad
21
Advice (from Xilinx)

• Dont overconstrain
• No more speed than you need
• Makes sense, but we dont have much feel for how
  far we can push these devices

22
Chipscope

• Works like logic analyzer using part of FPGA and
  some block RAMs
• Two components
• Core that you insert also need to setup the
  signals to act as triggers and to view
• Run time viewer
• Youll need to install software

23
New Source
24
Chipscope appears

• Double click to open

25
Triggers
Have only tried one
Number of trigger signals
More complex takes more logic
Match Unit is a comparator
26
Depth
27
Making Connections (1)
28
Connections(2)
29
Connections (3)
30
Keep Hierarchy

• Turn on Advanced Dialog options
• Edit -gt Preferences
• Processes Tab
• Right click on Synthesize
• Click Keep Hierarchy

31
Run Time Demo

• Probe JTAG chain
• Import signal names
• Setup trigger conditions
• Run
• Will wait for trigger conditions to be met
• Then capture
• You can change the way data displayed
• Group signals into buses also