MOS Inverters

1
MOS Inverters

• Introduction
• Static

2
Introduction

• Inverter

Vout
Vin
Symbol
Vout
Truth Table
VDD
Logic-1
Logic-0
VDD Vin
Ideal Inv. Transfer Char.
3
Process (1)
4
Process (2)
Self-Align Doping
5
Process (3)
field oxide metal-poly insulator thin oxide
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Process (4)
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Process (Inverter)
In
GND
VDD
Legend of each layer
N-well
P-diffusion
N-diffusion
Polysilicon
Metal
contact
8
Layout and Cross-Section View of Inverter
Inverter
Top View or Layout
VDD
In
GND
VDD
In
Out
Out
GND
Cross-Section View
Legend of each layer
N-well
P-diffusion
N-diffusion
Polysilicon
Metal
Source Prof. syhuangs note
contact
9
Simplified CMOS Process Flow
Create n-well and active regions
Grow gate oxide (thin oxide)
Deposit and pattern polysilicon layer
Implant source and drain regions, substrate
contacts
Source Prof. syhuangs note
Create contact windows, deposit and pattern metal
layers
10
N-well, Active Region, Gate Oxide
Top View
Cross Section
Source Prof. syhuangs note
11
Polysilicon Layer
Top View
Cross-Section
Source Prof. syhuangs note
12
N and P Regions
Top View
Cross-Section
Ohmic contacts
Source Prof. syhuangs note
13
SiO2 Upon Device Contact Etching
Top View
Cross-Section
Source Prof. syhuangs note
14
Metal Layer by Metal Evaporation
Top View
Cross-Section
Source Prof. syhuangs note
15
A Complete CMOS Inverter
Top View
Cross-Section
Source Prof. syhuangs note
16
Enhancements
Three process enhancements to reduce interconnect
resistance of poly (R 20 40 W/square) -
Silicide silicon tantalum for gate material
(R 1 5 W/square) - Polycide silicide upon
polysilicon - Salicide (Self Aligned SILICIDE)
Source Prof. syhuangs note
Silicide
Polycide
Salicide
17
Design Rules

• Constraints of layout to avoid Fab. failure
• Gateway between Design and Fabrication
• Violation is likely to cause error(s)
• Three areas
• Minimum spacing avoid short between layers
• Minimum width to avoid break (open)
• Enclosure or extension for overlapping
• Micron rules the constraints are in micrometers

18
Design Rules (1)

• Lambda rules constraints are in terms of l,
• Parameter l (0.5 Min. distance)
• more scalable but less area efficient
• Design rule Check
• Automatically check design rule violations
• Warn designer of possible errors.
• Electrical Rule Check
• Automatically check electrical rule violations
• VDD shorts to Gnd, Floating nodes, etc.

19
Design Rule Illustration
Source Prof. syhuangs note
20
Substrate Well Contacts
Source Drain Contacts - surrounded by p
region in the n-well - surrounded by n region
in the p-substrate N-well Contacts -
surrounded by n region in the n-well -
connect n-well to VDD Substrate Contacts -
surrounded by p region in the p-substrate -
connect p-substrate to GND Many substrate well
contacts are needed to avoid latch-up problem,
sometimes form a guard-ring
Source Prof. syhuangs note
21
Latchup Problem
Two parasitic NPN PNP transistors form a
positive feedback loop, once activated, will
cause short-circuit effect from VDD to GND and
lead to self-destruction of the device.
Equivalent Circuit
PNP
NPN
Solutions guard-rings to reduce Rsubstrate and
Rwell, increase the space
between n-well NMOS,
Source Prof. syhuangs note
22
Silicon On Insulator (SOI)
Disadvantages - more expensive - process is
less developed - lower yield
Advantages - denser (absence of wells) - could
be faster (lower substrate capacitance) - no
latch-up problem - enhanced radiation tolerance
sapphire
???
Source Prof. syhuangs note
23
Drain I-V Before Pinch-Off
Assumptions (before pinch-off)
Peak at VDSVGS-VT0
k process parameters where Cox e /
tox W/L design parameter
Source Prof. syhuangs note
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Saturation Current
Source Prof. syhuangs note
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Saturation Current v.s. Gate Voltage
Source Prof. syhuangs note
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Channel Length Modulation (I)
When VDS gt VDSAT (i.e., VGS-VT) Channel voltage
at pinch-off point (i.e., L) remains VDSAT
Source Prof. syhuangs note
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Channel Length Modulation (II)
L L - DL
l is called channel length modulation coefficient
( 0.1 to 0.005 V-1)
Source Prof. syhuangs note
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Channel Length Modulation (III)
Drain Current
Drain Voltage
Source Prof. syhuangs note
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SPICE DC Parameters
Representative values for 1m n-well CMOS process
Source Prof. syhuangs note
30
Other Effects

• Subthreshold Region
• Cutoff region is also referred to as subthreshold
  region
• IDS, though very small, increases exponentially
  with VGS and VDS
• Used for building special purpose circuit (e.g.,
  neural network)
• Fowler-Nordheim Tunneling
• Current from gate to channel when gate-oxide is
  very thin
• Limits the thickness of the gate oxide as devices
  shrink
• Of great use in programmable logic devices (e.g.,
  FLASH)

Source Prof. syhuangs note
31
Other Effects(2)

• Drain Punchthrough
• Depletion region around the drain extends to the
  source under large VD
• Hot-Electrons
• Short-channel in submicron device, hot electrons
  occur due to the strong electric field at the
  drain side
• Inject into the gate-oxide, causing device
  degradation (VT, k)

Source Prof. syhuangs note
32
Short-Channel Effect

• In deep-submicron devices,
• channel length the same order of magnitude as
  the the depletion region thickness of the source
  and drain junctions.
• VT0 (short-channel) VT0 DVT0 (short-channel
  effect)

Source Prof. syhuangs note
33
VT Reduction Due to Short Channel
Source Prof. syhuangs note
34
Narrow-Channel Effect

• A device is defined to have a narrow channel if
  channel width W is on the same order of magnitude
  as the maximum depletion region thickness xdm
• VT tends to increase due to the shallow depletion
  region charge underneath the GATE-to-FOX overlap
  area, QNC

Source Prof. syhuangs note
35
Hot-Carrier Injection

• In small-geometry devices,
• carrier has a higher kinetic energy, and thus
  might be able to inject into the thin-oxide area
• resulting a higher VT, thereby a lower
  transconductance
• causing a reliability problem

36
Oxide Damage Due to Hot-Carrier
Source Prof. syhuangs note
37
Device Scaling (Shrinking)
Types (1) Full Scaling (2) Constant Voltage
Scaling
New generation for every 2 3 years S Scaling
factor (1.2 1.5 from one generation to the
next)
Source Prof. syhuangs note
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Full Scaling (Constant-Field Scaling)
Physical dimensions 1/S Power Supply 1/S Doping
Density S
Power density unchanged
Source Prof. syhuangs note
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Constant Voltage Scaling
Physical dimensions 1/S Power Supply 1 Doping
Density S2
Power density Increase by S3 !
Source Prof. syhuangs note