ALU

1
Buss
enaPC
enaMARM
16
Buss
16
MARMuxOut
PC
DR
16
16
3
SR1
3
Reg File
IR
MARMux
PC
selPC
SR2
2
8
3
regWE
clk
selMAR
clk
reset
ldPC
eabOut
16
reset
PC
16
selEAB1
EAB
selEAB2
Rb
Ra
2
16
16
Ra
IR
16
10
10
IR
6
N
Z
P
ALU
aluControl
2
ldIR
IR
clk
IR
NZP
regWE
aluOut
16
reset
16
enaALU
Buss
16
Buss
enaMDR
16
2
LC3 Datapath
IR
N,Z,P
Programmed Memory
Control SIgnals
3
LC3 Datapath
IR
N,Z,P
Programmed Memory
Control SIgnals
4
LC3 Datapath
IR
N,Z,P
Programmed Memory
Control SIgnals
5
Viewing Signals Which are Buried Inside of
Hierarchical Blocks
MM0
PC0
RF0
EAB0
aluIn2
ALU0
add wave /ALU0/aluIn2
6
Nested DO Files
Inactive.DO Set all of the signals that drive
onto the bus or load registers to their
inactive states force enaALU 0 force enaMARM
0 force enaPC 0 force ldPC 0 force ldIR 0 force
ldMAR 0 force ldMDR 0 force regWE 0 force memWE
0 force enaMDR 0 force reset 0
Fetch.DO deactivate all signals do
Inactive.DO load the MAR (put force commands
here) run (for 1 clock cycle) read from memory
into MDR and increment the PC (put force
commands here) run (for 1 clock cycle) load
the IR (put force commands here) run (for 1 clock
cycle) deactivate all signals do Inactive.DO
7
Signals and Clock Edges
Clock
Reset
Ctrl1
Ctrl2
Ctrl3
run
run
run
run
run
run
run
Stop somewhere other than a clock edge
Run for exactly one clock cycle
8
From Now Till the End of the Semester

• You may work in teams of 2 or 3.
• Clearly mark the delineation of each instruction
  on your waveform and note what the instruction is
  after it is fetched into the IR
• Drop your marked up waveforms into the homework
  box.
•  
• This is still a lab. It requires a full write-up.
• Normal due dates apply.