VHDL introduction

1
VHDL introduction

• What is VHDL?
• Design methodology using VHDL
• Entities and Architectures
• VHDL modelling Concepts

2
What is VHDL?

• VHSIC Hardware Description Language
• Modelling Digital Electronic Systems
• supports concurrency
• International Standard
• IEEE Std 1076-1987
• IEEE Std 1076-1993
• Working on AHDL

3
VHDL Advantages

• Standard
• Government Support
• Industry Support
• Portability
• Modelling Capability
• Reusablity
• Technology independent
• Documentation

4
Design Levels
Architectural Level
Behavioural Synthesis
Behavioural Level
Behavioural Synthesis
Register Transfer Level
Logic Synthesis
G
ate Level
Technology Mapping
C
ircuit Level
Place and Route
L
ayout Level
5
Design methodology using VHDL
6
Testing - Testbench

• Vectors can be generated
• Statically
• Dynamically

Design Under Test (dut)
Testbench
7
Board Level Simulation
Board

• Purchase commercial models
• Design can also contain custom components
• Completely verify design before manufacture

CPU
I/O
Memory
ASIC/ FPGA