ECE 406

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ECE 406 Design of Complex Digital Systems
Lecture 8 Sequential Design
Spring 2007 W. Rhett Davis NC State
University with significant material from Paul
Franzon, Bill Allen, Xun Liu
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Design Example

• Design a module named ALU.
• It has three 3-bit inputs A, B, and C and a 1-bit
  input E.
• It has a 3-bit output R and a 1-bit output O.
• When E is 1,
• R is the bit-wise XOR of A and B, and
• O is 1.
• When E is 0,
• R is the sum of B and C (both are assumed to be
  signed integers), and
• O is the non-overflow indicator, which is 0 when
  signed overflow happens.

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ALU data flow

• module ALU (
• output 20 R,
• output O,
• input 20 A,
• input 20 B,
• input 20 C,
• input E
• )
• wire 30 Sum
• assign Sum B C
• assign O ( E1 ? 1 Sum3Sum2 )
• assign R ( E1 ? A B Sum20 )
• endmodule

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ALU procedural

• module ALU (
• output reg 20 R,
• output reg O,
• input 20 A,
• input 20 B,
• input 20 C,
• input E
• )
• reg 30 Sum
• always _at_(A or B or C or E)
• begin
• Sum B C
• if (E1)
• begin
• O 1
• R A B
• end
• else
• begin

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Todays Lecture

• Flip-Flops, Blocking vs. Non-Blocking
  Assignments
• Sequential Design w/ Simplified Coding Style
• Sophisticated Coding Style

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Inferring Hardware from Assignments

• When given an always_at_(posedge clock) behavior and
  asked to draw a schematic, I follow these
  steps
• For every left-hand side of an assignment, draw a
  flip-flop whose output is connected to that
  signal
• For non-blocking assignments (lt), set the input
  of each flip-flop to be the right-hand side of
  the last assignment for each variable
• For blocking assignments (), work back from the
  end to figure out the inputs to the flip-flops
• When writing your own behavior, it is suggested
  that you use non-blocking assignments (lt), so
  that you dont have to work back from the end.

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Example

• reg A, B, C, D
• always_at_(posedge clock)
• begin
• C A
• B C
• C D
• end

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Example

• reg A, B, C, D
• always_at_(posedge clock)
• begin
• C lt A
• B lt C
• C lt D
• end

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Example

• reg A, B, C, D
• always_at_(posedge clock)
• begin
• if (A)
• D lt B
• else
• D lt C
• C lt D
• end

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Todays Lecture

• Flip-Flops, Blocking vs. Non-Blocking
  Assignments
• Sequential Design w/ Simplified Coding Style
• Sophisticated Coding Style

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Design Process

• Step 1 Write Specification
• Step 2 Draw Schematic
• Step 3 Write Verilog Code

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Step 1 Write Specification

• Example Count Down Timer from the Verilog
  Simulation Tutorial
• 4-bit counter
• count value loaded from in on a positive clock
  edge when latch is high
• count value decremented by 1 on a positive clock
  edge when dec is high
• count value cleared when clear is high
• decrement stops at 0
• zero flag active high whenever count value is 0

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Step 2 Draw a Block Diagram

• Identify from the Specification
• Ports
• Registers
• Datapath Logic
• MUXes
• Control Logic
• ALWAYS DRAW A BLOCK DIAGRAM OR SCHEMATIC BEFORE
  CODING

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Identify Ports

• 4-bit counter
• count value loaded from in on a positive clock
  edge when latch is high
• count value decremented by 1 on a positive clock
  edge when dec is high
• count value cleared when clear is high
• decrement stops at 0
• zero flag active high whenever count value is 0

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Identify Registers

• 4-bit counter
• count value loaded from in on a positive clock
  edge when latch is high
• count value decremented by 1 on a positive clock
  edge when dec is high
• count value cleared when clear is high
• decrement stops at 0
• zero flag active high whenever count value is 0

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Identify Datapath Logic

• 4-bit counter
• count value loaded from in on a positive clock
  edge when latch is high
• count value decremented by 1 on a positive clock
  edge when dec is high
• count value cleared when clear is high
• decrement stops at 0
• zero flag active high whenever count value is 0

• How would you implement the 0? logic?

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Identify MUXes

• 4-bit counter
• count value loaded from in on a positive clock
  edge when latch is high
• count value decremented by 1 on a positive clock
  edge when dec is high
• count value cleared when clear is high
• decrement stops at 0
• zero flag active high whenever count value is 0

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Identify Control Logic

• 4-bit counter
• count value loaded from in on a positive clock
  edge when latch is high
• count value decremented by 1 on a positive clock
  edge when dec is high
• count value cleared when clear is high
• decrement stops at 0
• zero flag active high whenever count value is 0

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Step 3 Write the Verilog Code

• Name the internal signals
• Write the description into code
• Ports internal signals
• Registers
• Datapath Logic
• MUXes
• Control Logic
• Never write a piece of code if you cant
  visualize the logic that it implements

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Simplified Verilog Style

• Verilog is a powerful and flexible language
• It is very easy to describe functions that do NOT
  map well (or synthesize into) hardware
• Constrain yourself to a subset of the language
  and a specific style of usage

• Registers
• always_at_(posedge clock)
• begin
• register_output1 lt register_input1
• register_output2 lt register_input2
• end

• MUXes and Control Logic
• always_at_(input1 or input2 or ...)
• begin
• ltif-then-else or case statementgt
• end

Datapath Logic assign output ltinputs and
operatorsgt
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Name the Internal Signals
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Complete Verilog Code

• module counter (clock, in, latch, dec, clear,
  zero)
• / simple top down counter with zero flag /
• input clock / clock /
• input 30 in / starting count /
• input latch / latch in when high /
• input dec / decrement count when dec
  high /
• input clear / clear count when clear
  high /
• output zero / high when count down to
  zero /
• reg 30 value / current count value /
• reg 30 next_value
• wire zero, enable
• // D-Flip Flops with enable
• always_at_(posedge clock)
• if (enable) value lt next_value
• // produce enable

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always_at_(posedge clock) if (enable) value lt
next_value assign enable latch (dec
!zero) clear always_at_(latch or value or in or
dec or zero) begin if (latch) next_value
in else if (dec !zero) next_value value
- 1b1 else next_value 4b0 // default is
clear end assign zero value
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Todays Lecture

• Flip-Flops, Blocking vs. Non-Blocking
  Assignments
• Sequential Design w/ Simplified Coding Style
• Sophisticated Coding Style

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Sophisticated Style

• Combine registers and as much combinational logic
  as you can into one always_at_(posedge clock) block

always_at_(posedge clock) begin if (latch)
value lt in else if (dec !zero) value lt
value - 1b1 else value lt 4b0 // default
is clear end assign zero value
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Comparison of Styles
Simplified Style Sophisticated Style
How many internal signals needed to be defined?
How many lines of code? (including spaces)
How many separate always blocks and assign statements?
With the Sophisticated style, youll write
descriptions faster.
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Comparison of Styles
Simplified Style Sophisticated Style
How can you tell from the code where the flip-flops are?
Do you need to worry about whether an assignment is blocking or non-blocking?
With the Sophisticated style, its easier to make
errors in your code
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Summary

• How do you infer flip-flops for an
  always_at_(posedge clock) procedure with blocking or
  non-blocking assignments?
• Is it better to use blocking or non-blocking
  assignments in an always_at_(posedge clock)
  procedure? Why?
• What are the key elements of the simplified
  coding stlye?
• What Verilog constructs do you use to describe
• MUXes
• Control logic
• Datapath logic
• Registers
• What would happen if you assigned the zero
  signal inside the always_at_(posedge clock) block in
  the sophisticated style example?