ECE 406

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ECE 406 Design of Complex Digital Systems
Lectures 12- LC-3 Micro-architecture
Spring 2007 W. Rhett Davis NC State
University with significant material from Paul
Franzon, Bill Allen, Xun Liu
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Microarchitecture

• The von Neumann Model
• Memory
• Processor
• Input
• Output
• Control

memory
input
output
processor
control
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What Blocks Do We Need?

• Instructions
• ADD
• AND
• NOT
• BRx
• JMP/RET
• JSR
• JSRR
• LD
• ST
• LDR
• STR
• LDI
• STI

• ALU
• Register File
• Program Counter
• Status Register
• Instruction Register
• Logic to direct operands to/from ALU
• Logic to interface to Memory

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Conventions

• Control signals are omitted for simplicity
• Makes the diagram easier to read
• Usually far fewer control signals than data
  signals
• Wire bundles
• A set of nets going from one block to another is
  represented as
• When a set of nets contains signals that go in
  both directions (both input and output for a
  block), we use
• A set of nets on a shared bus (a bus with
  multiple drivers) is represented as
• If a block only reads or writes one signal on a
  shared bus, we use

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Simplified LC3 Microarchitecture
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Detail of Memory Bus
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Controller

• Maintains the master state-machine for the system
• Distributes this state to the rest of the system
  (not shown)

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Fetch

• Maintains the program counter (PC) for the system
• Communicates with Memory to make sure instruction
  is made available to Decode block
• Master of the shared Memory bus during the all
  states but the Read Memory, Write Memory, and
  Indirect Address Read states.
• Receives the next address from the Execute block
  (if a branch is taken)

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Decode

• Maintains the Register File (R0R7) for the
  system
• Maintains Instruction Register (IR) and
  Processor Status Register (PSR)
• Receives instruction word from Main Memory
• Provides operands to Execute and MemAccess blocks
• Receives the value to write-back to the RegFile
  from the Writeback block
• Decodes every instruction and provides control
  signals to most blocks (not shown)

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Execute

• Directs operands from the Decode block to the
  Arithmetic Logic Unit (ALU)
• Sends result to the Writeback block (for storage
  in Register File), or Fetch block (with the next
  address on a branch)

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MemAccess

• Receives Address to be read/written from Execute
  block
• Receives Data to be written from Decode block
• Master of the shared Memory bus during the Read
  Memory, Write Memory, and Indirect Address
  Read states.
• Provides Data read from Memory to Writeback block

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Writeback

• Decides which value will be written back to the
  Register file
• Receives output of ALU from Execute Block
• Receives contents of MDR from MemAccess Block
• Sends result to Decode Block for storage in
  Register File

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Simplified State Machine
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Execution of ADD/AND/NOT

1. Fetch Unit loads instruction from memory
2. Decode Unit determines the operands
3. Execute Unit applies operands to ALU
4. Result stored in Register File
5. PC incremented

1
2
5
3
4
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Execution of BRx/JMP/RET

1. Fetch
2. Decode
3. Execute computes new PC
4. PC updated

1
2
4
3
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Execution of JSR/JSRR

1. Fetch
2. Decode
3. Execute computes new PC
4. PC stored in R7
5. PC updated

1
2
5
3
4
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Execution of LD/LDR

1. Fetch
2. Decode
3. Execute Unit computes address
4. MemAccess Unit reads Memory
5. Write to Register File
6. PC incremented

1
2
6
3
4
5
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Execution of ST/STR

1. Fetch
2. Decode
3. Execute Unit computes address
4. MemAccess Unit writes Memory
5. Update PC

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2
5
3
4
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Execution of LDI

1. Fetch
2. Decode
3. Compute address
4. Read Memory for Indirect Address
5. Read Memory
6. Update Register File
7. PC incremented

1
2
7
3
4
5
6
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Execution of STI

1. Fetch
2. Decode
3. Compute address
4. Read Memory for Indirect Address
5. Write to Memory
6. Update PC

1
2
6
3
4
5
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Execution of LEA

1. Fetch
2. Decode
3. Compute address
4. Update Register File
5. Update PC

1
2
5
3
4
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Control Signal Tables

• It helps greatly in the debugging of the LC-3
  System to have completed tables that give the
  values of various control signals, depending on
  the instruction that is being executed.
• In this section, we will begin to fill out these
  tables.
• The instruction-set specification is needed to
  complete these tables, and is included here for
  convenience.

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ALU Operations
15 12 11 9 8 6 5 4
3 2 0

• ADD
• AND
• NOT

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Control Instructions
15 12 11 9 8 6 5 4
3 2 0

• BR
• JMP
• JSR
• JSRR
• RET
• RTI
• TRAP

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Load/Store Instructions
15 12 11 9 8 6 5 4
3 2 0

• LD
• LDR
• LDI
• LEA
• ST
• STR
• STI

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Complete the Table
C_Control C_Control C_Control C_Control
Operation mode Instr. Type Store PC Mem. Access Mode load
ADD 0
1
AND 0
1
NOT
BR
JMP/RET
JSR
JSRR
LD
LDR
LDI
LEA
ST
STR
STI
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Fetch Module Inputs Outputs

• Input Signals
• clock global system clock.
• reset when high, the PC should be synchronously
  set to x3000
• state the state from the Controller block.
• taddr150 the next value of the PC if a
  branch is taken.
• br_taken signal to indicate that a branch is
  taken.
• Output Signals
• rd signal to indicate to the Memory that a read
  is to be performed, rather than a write. This
  signals should be high-impedence during the Read
  Memory, Write Memory, and Indirect Address
  Read states, because the MemAccess block will
  drive the shared bus during these cycles. In all
  other states, this signal should be high.
• pc the current value of the program counter,
  but should be high-impedence at the same times
  that the rd signal is high-impedence.
• npc should always be PC1.

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Fetch Block Sketch
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Complete the Table

Operation mode br_taken
ADD 0
1
AND 0
1
NOT
BR
JMP/RET
JSR
JSRR
LD
LDR
LDI
LEA
ST
STR
STI
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Execute Block Sketch
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Complete the Table
E_Control E_Control E_Control E_Control E_Control
Operation mode ALU Op Sel ALU Op Sel PC Sel 1 PC Sel 2 OP 2 Sel
ADD 0
1
AND 0
1
NOT
BR
JMP/RET
JSR
JSRR
LD
LDR
LDI
LEA
ST
STR
STI
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MemAccess

• Receives Address to be read/written from Execute
  block
• Receives Data to be written from Decode block
• Master of the shared Memory bus during the Read
  Memory, Write Memory, and Indirect Address
  Read states.
• Provides Data read from Memory to Writeback block

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Detail of Memory Bus
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MemAccess Signals

• What is meant by the M_Data signal? Why does it
  come from the Decode block?
• What is meant by the M_Addr signal? Why does it
  come from the Execute block?
• What is meant by the memout signal?

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MemAccess States
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Read Memory State LD, LDR

• Determine the Memory Bus Signals
• rd
• addr
• din

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Write Memory State ST, STR

• Determine the Memory Bus Signals
• rd
• addr
• din

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Read Indirect Address State LDI, STI

• Determine the Memory Bus Signals
• rd
• addr
• din

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Example LDI

• Location of Indirect Address 16h300A
• Indirect Address 16h3010
• Value Stored at Indirect Address 16h1234

Note that dout is the same as addr
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Example STI

• Location of Indirect Address 16h300A
• Indirect Address 16h3010
• Value to be Stored at Indirect Address 16h1234

Note that dout is the same as addr
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Read Indirect Address State

• During this state, what will dout be set to?
• What needs to happen to this value on the next
  cycle?
• How can we ensure that this happens?

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Read/Write Memory States Revisited

• Read State Memory Bus Signals
• rd
• addr
• din

• Write State Memory Bus Signals
• rd
• addr
• din

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Verilog Code for MemAccess

• Read Memory State
• if(M_Control0) addrltM_Addr else
  addrltdout
• dinlt16'h0 // dont care
• rdlt1'b1
• Read Indirect Address State
• addrltM_Addr
• dinlt16'h0 // dont care
• rdlt1'b1

• Write Memory State
• if(M_Control0) addrltM_Addr else
  addrltdout
• dinltM_Data
• rdlt1'b0
• All Other States
• addrlt16'hz
• dinlt16'h0 // dont care
• rdlt1'bz

Remember that this is combinational logic!
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Complete the Table

Operation mode M_Control
ADD 0
1
AND 0
1
NOT
BR
JMP/RET
JSR
JSRR
LD
LDR
LDI
LEA
ST
STR
STI
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What about memout?

• memout needs to present the value read from
  memory to the Writeback block.
• Theres really no reason why it cant just be
  connected to dout permanently (with an assign
  statement).
• assign memout dout

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Writeback

• Decides which value will be written back to the
  Register file
• Receives output of ALU from Execute Block
• Receives contents of Memory from MemAccess Block
• Sends result to Decode Block for storage in
  Register File

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Writeback
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Writeback

• For which instructions will the following be
  written to the Register File?

aluout pcout npc memout
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Complete the Table

Operation mode W_Control
ADD 0
1
AND 0
1
NOT
BR
JMP/RET
JSR
JSRR
LD
LDR
LDI
LEA
ST
STR
STI

• I suggest updating this table with the actual MUX
  input values once you have written the complete
  Verilog Code
• It will make the design of the Decode Block
  easier

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Decode

• Maintains the Register File (R0R7) for the
  system
• Maintains Instruction Register (IR) and
  Processor Status Register (PSR)
• Receives instruction word from Main Memory
• Provides operands to Execute and MemAccess blocks
• Receives the value to write-back to the RegFile
  from the Writeback block
• Decodes every instruction and provides control
  signals to most blocks (not shown)

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What is a Register File?

• A register file is usually a block of memory that
  allows two reads and one write in the same cycle.
• Do the reads and writes need to be in the same
  cycle?

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Conceptual Model of a RegFile
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Write the Code for this RegFile

• Easier to write with a memory array, rather than
  8 registers.

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Difficulty with this Model

• Most waveform formats dont store contents of
  memory.
• If you want to view results in SimVision, youll
  need to do the following
• Doesnt affect synthesis results. (Why not?)
• Note This is unnecessary with the NC-Verilog GUI

• wire 150 R0,R1,R2,R3,R4,R5,R6,R7
• assign R0ram0
• assign R1ram1
• . . .

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Complete the Table
Operation mode DR SR1 SR2
ADD 0
1
AND 0
1
NOT
BR
JMP/RET
JSR
JSRR
LD
LDR
LDI
LEA
ST
STR
STI
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Examining Overall System Timing

• How do you get all of the blocks in the system to
  talk to each other correctly?
• (How to make sure that the right signal gets to
  the right place at the right time?)
• List all of the memory elements in the LC3
  Microcontroller
• How do we expect these memory elements to evolve
  over time?

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Synchronous Timing Methodology

• Assume all memory elements are triggered on the
  rising edge of the clock
• There should only be combinational logic between
  memory elements.
• The output of each memory element passes through
  the combinational logic and sets up the input on
  the next memory element on the next clock edge

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Portion of Lecture 11 Code
16h3000 and r0, r0, 0 (5020) Initialize r0 to
0 16h3001 add r0, r0, 7 (1027) Load 7 in
r0 16h3003 and r1, r1, 0 (5260) Initialize
r1 to 0 16h3003 add r1, r1, 5 (1265) Add 5
to r1 16h3004 add r0, r0,-1 (103F) Decrement
r0 16h3005 brp -3 (03FD) Repeat until r0 is
zero 16h3006 st r1, 2 (3202) Store result
(35) in var1 16h3007 lea r6, 4 (EC04) Load
16h020B in r6 16h3008 jmp r6 (C180) Jump to
16h020B 16h3009 var1 (0000) 16h300A
var2 (0000) 16h300B var3
(0000) 16h000C
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How does the state evolve?
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Preliminary Decode Schematic
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Problem with this Schematic

• With this schematic, the system state wont
  evolve as shown on previous slides. Why not?
• How can we fix this?

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Controller State Machine
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Fix the Schematic
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Top-Level Schematic