Verilog and VeriWell

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Verilog and VeriWell

• Bo Cheng

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Resources
http//www.asic-world.com/verilog/tools.html
http//www-inst.eecs.berkeley.edu/cs61c/resources
/verilogTutorial.pdf
http//www-ee.eng.hawaii.edu/sasaki/EE361/Fall04/
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Veriwell Tool

• Free verilog simulators
• Acquired by syncad
• Syncad offers verilog and other HDL tools. In
  particular, they have FREE demonstration verilog
  simulation tool called Verilogger Pro.

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Veriwell Installation
C\Program Files\VeriWell\exe
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Two-input Multiplexor Example
module mux2 (in0, in1, select, out) input
in0,in1,select output out wire
s0,w0,w1 not (s0, select) and (w0, s0,
in0), (w1, select, in1) or (out, w0,
w1) endmodule // mux2
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Testing the Multiplexor
module testmux reg a, b, s wire f reg
expected mux2 myMux (.select(s), .in0(a),
.in1(b), .out(f)) initial begin 0 s0 a0
b1 expected0 10 a1 b0 expected1 10
s1 a0 b1 expected1 10 finish end initia
l monitor( "selectb in0b in1b outb,
expected outb timed", s, a, b, f, expected,
time) endmodule // testmux
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Notation

• initial keyword to say that everything in the
  following block should be done once at the start
  of simulation.
• n
• By default, the unit of time is the nanosecond
  (ns).
• In testmux, the first set of assignments are made
  at 0ns from the start of simulation, the second
  at 10ns from the previous, etc.
• finish exits the simulator back to the operating
  system.

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Syntax
http//www.doe.carleton.ca/shams/97350/PetervrlK.
pdf

• A reg is a Verilog variable type and does not
  necessarily imply a physical register.
• A wire represents a physical wire in a circuit
  and is used to connect gates or modules.
• Declare input, output and bidirectional ports of
  a module or task.

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display, strobe, monitor

• display their values as text on the screen during
  simulation.
• display and strobe display once every time they
  are executed
• strobe displays the parameters at the very end
  of the current simulation time unit.
• monitor displays every time one of its
  parameters changes.
• The format string is like that in C/C, and may
  contain format characters.
• Format characters include d (decimal), h
  (hexadecimal), b (binary), c (character), s
  (string) and t (time).

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time, stime, realtime

• These return the current simulation time as a
  64-bit integer, a 32-bit integer, and a real
  number, respectively.

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Adding Delay to the Multiplexor Example
module mux2 (in0, in1, select, out) input
in0,in1,select output out wire s0,w0,w1 not 1
(s0, select) and 1 (w0, s0, in0), (w1, select,
in1) or 1 (out, w0, w1) endmodule // mux2
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module testmux2 reg 20 c wire f reg
expected mux2 myMux (.select(c2), .in0(c0),
.in1(c1), .out(f)) initial Begin 0 c
3b000 expected1b0 repeat(7) begin 10 c
c 3b001 if (c2) expectedc1 else
expectedc0 end 10 finish end initial begi
n display("Test of mux2.") monitor("select
in1 in0b outb expectedb timed",
c, f, expected,
time) end endmodule // testmux2
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Building a Circuit Hierarchy
//4-input multiplexor built from 3 2-input
multiplexors module mux4 (in0, in1, in2, in3,
select, out) input in0,in1,in2,in3 input 10
select output out wire w0,w1 mux2 m0
(.select(select0), .in0(in0), .in1(in1),
.out(w0)), m1 (.select(select0), .in0(in2),
.in1(in3), .out(w1)), m3 (.select(select1),
.in0(w0), .in1(w1), .out(out)) endmodule // mux4