Sistemi Elettronici

1

2
SEQUENTIAL LOGIC
3
Sequential Logic
4
Positive Feedback Bi-Stability
5
Meta-Stability
Gain should be larger than 1 in the transition
region
6
SR-Flip Flop
Q
Q
R
S
Q
Q
S
Q
1
Q
1
Q
Q
R
0
1
1
0
1
0
0
1
0
1
0
1
7
JK- Flip Flop
8
Other Flip-Flops
9
Race Problem
10
Master-Slave Flip-Flop
11
Propagation Delay Based Edge-Triggered
12
Edge Triggered Flip-Flop
13
Flip-Flop Timing Definitions
14
Maximum Clock Frequency
15
CMOS Clocked SR- FlipFlop
16
Flip-Flop Transistor Sizing
17
6 Transistor CMOS SR-Flip Flop
18
Charge-Based Storage
19
Master-Slave Flip-Flop
20
2 phase non-overlapping clocks
21
2-phase dynamic flip-flop
22
Flip-flop insensitive to clock overlap
23
C2MOS avoids Race Conditions
24
Pipelining
25
Pipelined Logic using C2MOS
26
Example
27
NORA CMOS Modules
28
Doubled C2MOS Latches
29
TSPC - True Single Phase Clock Logic
30
Master-Slave Flip-flops
31
Schmitt Trigger

• VTC with hysteresis
• Restores signal slopes

32
Noise Suppression usingSchmitt Trigger
33
CMOS Schmitt Trigger
Moves switching threshold of first inverter
34
Schmitt TriggerSimulated VTC
35
CMOS Schmitt Trigger (2)
36
Multivibrator Circuits
37
Transition-Triggered Monostable
38
Monostable Trigger (RC-based)
39
Astable Multivibrators (Oscillators)
40
Voltage Controller Oscillator (VCO)
41
Relaxation Oscillator