Title: Sistemi Elettronici
1 2COMBINATIONAL LOGIC
3Overview
4Combinational vs. Sequential Logic
5Static CMOS Circuit
6Static CMOS
7NMOS Transistors in Series/Parallel Connection
Transistors can be thought as a switch controlled
by its gate signal NMOS switch closes when switch
control input is high
8PMOS Transistors in Series/Parallel Connection
9Complementary CMOS Logic Style Construction
(cont.)
10Example Gate NAND
11Example Gate NOR
12Example Gate COMPLEX CMOS GATE
134-input NAND Gate
Vdd
Out
GND
In1
In2
In3
In4
14Standard Cell Layout Methodology
15Two Versions of (ab).c
16Logic Graph
17Consistent Euler Path
18Example x abcd
19Properties of Complementary CMOS Gates
20Transistor Sizing
21Propagation Delay Analysis - The Switch Model
22What is the Value of Ron?
23Numerical Examples of Resistances for 1.2mm CMOS
24Analysis of Propagation Delay
25Design for Worst Case
26Influence of Fan-In and Fan-Out on Delay
27tp as a function of Fan-In
28Fast Complex Gate - Design Techniques
29Fast Complex Gate - Design Techniques (2)
30Fast Complex Gate - Design Techniques (3)
31Fast Complex Gate - Design Techniques (4)
32Example Full Adder
33A Revised Adder Circuit
34Ratioed Logic
35Ratioed Logic
36Active Loads
37Load Lines of Ratioed Gates
38Pseudo-NMOS
39Pseudo-NMOS NAND Gate
VDD
GND
40Improved Loads
41Improved Loads (2)
42Example
43Pass-Transistor Logic
44NMOS-only switch
45Solution 1 Transmission Gate
46Resistance of Transmission Gate
47Pass-Transistor Based Multiplexer
S
VDD
GND
In1
In2
S
48Transmission Gate XOR
49Delay in Transmission Gate Networks
50Elmore Delay (Chapter 8)
51Delay Optimization
52Transmission Gate Full Adder
53(2) NMOS Only Logic Level Restoring Transistor
54Level Restoring Transistor
55Solution 3 Single Transistor Pass Gate with VT0
56Complimentary Pass Transistor Logic
574 Input NAND in CPL
58Dynamic Logic
59Example
60Transient Response
61Dynamic 4 Input NAND Gate
VDD
Out
In1
In2
In3
In4
f
GND
62Reliability Problems Charge Leakage
63Charge Sharing (redistribution)
64Charge Redistribution - Solutions
65Clock Feedthrough
66Clock Feedthrough and Charge Sharing
67Cascading Dynamic Gates
68Domino Logic
69Domino Logic - Characteristics
70np-CMOS
71np CMOS Adder
72Manchester Carry Chain Adder
73CMOS Circuit Styles - Summary