FlipFlops: SR

1
Flip-Flops S-R

• Digital Logic
• Kleitz 10-2

2
Relay Maintaining Circuit
start
stop
L1
L2
C
Start Action Normally open. Normally kept low.
Press to get a high and turn on R.
Stop Action Normally Closed. Normally held
high. Press to get a low and turn off R.
C
3
Gate Maintaining Circuit

• Rename variables
• S set start.
• Assume a 1 on S will set.
• R reset stop.
• Assume a 1 on R will reset.
• Need opposite action button
• Q C output.

4

• S Set Start
• Assume a logic HIGH (1) will set.
• R Reset Stop
• Assume a logic HIGH (1) will reset.
• This is the opposite action of the N.C. button
  of the relay circuit.
• Need to invert the switch logic
• Q Output C (coil).

5
Gate Maintaining Circuit
6
Convert to NOR Gates
Bubble push the AND gate. Add inverter to NOR
gate to make OR gate.
7
Simplify
Remove duplicate inverters.
8
Cross NOR S-R Flip Flop
Redraw in typical layout.
9
S-R Timing Diagram
Set Hold NA Reset
NA Not allowed. Note Q and QNOT are both low.
10
Cross NOR S-R Flip-Flop

• Set Reset
• observe Q compliment output

Set
Q
Q
Reset
11
Set Operation

• Assume Q 0 initially.
• Make set 1 (briefly)
• The next Q will be high.

Set 1
0
Q 0
Q 1
Reset 0
12
Reset Operation

• Q goes to zero, Q goes to 1

Set 0
Q
Q
0
Reset 1
13
S-R Function Table
14
S-R Symbol
Note Q is on top, Q on bottom which is opposite
of the drawing of cross NOR circuit.
Most Common
Most Accurate
S Q R Q
S Q R Q
Q
15
S-R Timing

• Output remains even after input (S or R) is
  removed.
• Or, the output is latched.
• Useful for storage of data.
• This flip-flop is also transparent as the output
  changes immediately when the input changes.

16
S-R Timing Diagram
17
Clocked Gates

• Asynchronous
• a not
• syn with
• chronos time (clock)
• Asynchronous means the flip flop output responds
  immediately to input changes rather than waiting
  for a clock pulse.

18
Clocked Gates

• Synchronous
• Output responds to input changes only when
  enabled by a clock pulse.

Q
Q
19
Synchronous Advantage

• Inputs S and R may not change at exactly the
  right time.
• Suppose at present S1, R0. Then a reset is
  desired to S0, R1.
• If R changes before S, there is a momentary
  illegal state of S1, R1.
• Use clock enable to make sure inputs are settled
  to the proper values, then change the output.

20
Gated SR Flip Flop
21
Gated S-R Flip-Flop