FlipFlops

1
Flip-Flops

• Sequential Logic

2
Admin

• IT104A grades posted (Check Route Y)
• Bumped (upward) to compensate for extra credit
  quiz statistical distortions.
• Avg. C, Median B

3
Learning Outcomes

• Explain Combinational vs.Sequential
• RS flip-flop
• Clocked F/F
• Data (D), JK, T (Toggle) flip-flops
• Triggering edge vs. level
• Multivibrators

4
Circuits that dont work?

• NAND gates with cross-over feedback
• See Ouroboros at Wikipedia
• Call inputs SLOW,RLOW and outputs Q, Q
• Try draw truth table for 01, 10 11
• Gives SET, RESET and HOLD Previous state

5

• Use SLOW,RLOW 01, 10
• Use SLOW,RLOW 11 Qt-1 0, 1

6
SR flip-flop

• SLOW,RLOW 01 SET (Q1, Q0)
• SLOW,RLOW 10 RESET (Q0, Q1)
• SLOW,RLOW 11 HOLD (Q Q(t-1))
• SLOW,RLOW 00 (Q1, Q1 ? not useful
• System is both SET and RESET ? prohibited
• Textbook inverters in front of S R (fig 9-2
  or SET0 for SET etc.)

7
Sequential

• Combinational vs. Sequential definitions
• Implications
• Memory
• Depends on history

8
EG SR f/f

• Textbook errors
• figs 9-2, 9-3 Remove invert bobbles on S/R
  inputs or change table in fig 9-2
• EG prob 9.4 note that states go from a -gt j in
  time
• Problem with representing time-flow in
  English-reading (left-right) culture

9
Clocked SR

• Clocked SR fig 9-5
• What changed?
• Note inverted S/R inputs
• CLK1 ? same as S/R
• CLK0 same as S/R in HOLD
• Timing diagrams fig 9-6
• Eg problem 9.10, 9.13
• Synchronous (operates in step with clock)
• Still has Prohibited state SR1 in fig 9-5

10
Synchronized

• Already discussed combinational vs. Sequential
• Now we add Synchronous vs. Asynchronous
• Synchronous lock-step with a clock transition
• Asynchronous reacts immediately to an input
• Is combinational synch or asynch?

11
Data or Delay F/F

• D flip-flop
• Describe operation (next slide)
• Clocked SR with only SR10 or 01 possible
• Prohibited state not possible
• HOLD when CLK0
• Set and Clear inputs
• Often inverted
• Problems 9.16, 9.19,
• This is a one-bit REGISTER

12
Truth Table for D f/f
Q and Q will always have opposite states
Note Preset or Clr 1 means they are OFF. ?
is a clock transition Low ? High X is dont-care
13
JK f/f

• JK
• Fig 9-12, 9-13 (truth table), 9-15
• Adds toggle function when JK
• Toggle T f/f
• Can build other F/F circuits
• D F/F if JK.
• Preset (SET) and Clear (RESET) also available
• Prohibited inputs PRCLR0
• EG probs 9.25, 9.29, 9.30, 9.27

14
Triggering

• Data is set up when CLK is OFF
• Data transfers when CLK transitions to ON
• Data must be ready and stable before transition
• EDGE-Triggered
• Pulse-triggered also available
• (bubble on CLK symbol)
• Fig 9-21 data changes between pulses

15
Multivibrators

• Astable
• Produces train of pulses
• Simplest inverter feedback to own input
• Clocks
• Often controlled by RC timing circuits
• Famous 555 circuit (fig 9-23)
• Monostable
• Sends a single pulse
• Also called one-shot