TRD Electronics

1
TRD electronics Status and Planning

• Chip Status
• PASA Production/Testing
• TRAP Production/Testing
• MCM / RoB Production at FZK
• MCM / RoB Integration
• GTU status
• DCS status

Volker Lindenstruth Chair of Computer Science
Kirchhoff Institute for PhysicsUniversity
Heidelberg, Germany Phone [phone]
4303 Fax [phone] Email ti_at_kip.uni-heide
lberg.de WWW www.ti.uni-hd.de
2
Chip Status

• Very extensive tests performed
• Test infrastructure available for automatic
  testing of TRAP chips
• Three problems
• Second SCSN link dead (can be activated by
  writing one CSR word via SCSN link 1)
• QPM needs one cycle after write access and two
  cycles for read
• Digital filter power much higher than originally
  budgeted for due to error in measurement
  procedure
• Rest works nicely no additional issues fond
  even with extensive testing
• Oase dead short between PWR and GND no metal
  problem

3
Digital Filter Power ConsumptionTest Setup
Scenario 1
Scenario 2
Scenario 3
Filters stimulated by Event Buffer
Filters stimulated by ADCs
Noisy Baseline
Constant 0
Masked to 0
M. Gutfleisch
4
Digital Filter Power ConsumptionTest Input Data
Event 100 (measured on the chamber)
The noise has been scaled by 50 and by 25
Average Noise 2,70 ? 1,12
Event 50, Event 25
M. Gutfleisch
5
Digital Filter Power ConsumptionInitial
Measurements
Full Filter Functionality
Without Crosstalk Filter
Pedestal, Gain and Tail Filter
M. Gutfleisch
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Digital Filter Power ConsumptionTarget Baseline
Dependency
After pedestal correction all data is shifted to
a configurable target pedestal. If configured
inadequate, hits are detected permanently by the
preprocessor.
M. Gutfleisch
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Digital Filter Power ConsumptionProper Hit
Threshold
Full Filter Functionality
Without Crosstalk Filter
Pedestal, Gain and Tail Filter
M. Gutfleisch
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Digital Filter Power Consumption

• Power consumption reduced by adequate
  configuration set to 1.3 mA/ADC Channel
• Seperation of Charge Clusters (hits) from noisy
  Baseline crucial for low Power Consumption
• No implications on Copper Bus Bars but additional
  Power Supplies needed

9
Digital Filter Power Consumption Power/Copper
Implications

• Digital Power (1.8V) increased by 30
• 3456 A 4493 A
• For 54 Bus Bars
• 64 A 83 A
• (Copper Limit 140 A _at_ 1.8 V)

• Input used so far
• V. Angelov Power Consumption Estimates
• 886 mA/readout board

M. R. Stockmeier
10
PASA testing status

• Volume
• 98 wafers ( 120 000 chips)
• Testing features
• Peaking time
• Conversion gain
• Power-consumption
• Base-line level

• Testing schedule
• Start of testing Sep. 15
• 1 wafer ( 1200 chips)
• The remaining wafers over a two months period

PCI-interface
Data
Daughter board
Needle-head probe
Control
Mother board

• Infrastructure
• Needle-head prober is finished (works)
• Needle daughter board is finished and tested in
  august (works)
• An additional test structure for a stand alone
  test of a PASA with the test electronic is built.
  This will be tested before installation in the
  clean room at KIP.

H.C. Soltveit
11
TRAP MCM testing, MCM Production

• More than 30 MCMs produced and tested
• Good yield of a batch of 20 MCMs 18 worked, one
  was bad chip and one had a bonding problem
• Lot of 16 cannot be produced in one batch
• MPW Wafer caused problems at first

BGA socket developed at KIP
SCSN
NI - output
V. Angelov
12
Readout Board
13
GTU

• EDR passed got reviewer reply no surprises
• Architecture revised all modules defined
• Xilinx baseline
• OASE RX via MGT
• Module communication via DDR LVDS
• Backpline defined

J. Cuveland
14
2 GBit/s Link Comparison
J. Cuveland
15
PCB 1 Track Matching Unit (TMU)
3 Parallel Links (120 MHz DDR, 8 Bit LVDS)
12 Serial Links (2.4 GBit/s)
850 nm SFP-Transceiver
850 nm SFP-Transceiver
SRAM
Custom I/O
To Right TMU
850 nm SFP-Transceiver
2 MB
2 MB
2 MB
From Left TMU
850 nm SFP-Transceiver
To SMU Board
850 nm SFP-Transceiver
FPGA (Xilinx XC2VP40/50 FF1152)
850 nm SFP-Transceiver
From One Detector Stack
FPGA Size 47k/53k LCs, 692 I/Os
850 nm SFP-Transceiver
850 nm SFP-Transceiver
850 nm SFP-Transceiver
3,3V/5V PCI Bus Switches
850 nm SFP-Transceiver
CompactPCI
850 nm SFP-Transceiver
850 nm SFP-Transceiver
One Oscillator per TMU Board
Mezzanine Board Connector
J. Cuveland
16
PCB 2 GTU Backplane

• Backplane connects
• TMUs (interconnect for exchange of tracklet
  data)
• TMUs to SMU (uplink for trigger and raw data)
• All connections
• 8 Bit parallel LVDS (source-synchronous)
• 120 MHz DDR

SMU Board Connector
TMU Board Connector
TMU Board Connector
TMU Board Connector
TMU Board Connector
TMU Board Connector
J. Cuveland
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PCB 3 Supermodule Unit (SMU)
5 Parallel Links (120 MHz DDR, 8 Bit LVDS)
EEPROM, JTAG, ...
Uplink to Trigger Unit PCB
From TMU 0
Parallel Output
FPGA (e. g. Xilinx XC2V500 FG456)
Custom I/O
From TMU 1
From TMU 2
Ethernet RJ45
From TMU 3
From TMU 4
Detector Control System (DCS) Board
1 Serial Link (200 MByte/s)
CompactPCI
Detector Data Link (DDL) - Source Interface Unit
(SIU)
To DAQ
J. Cuveland
18
PCB 4 Trigger Unit (TU)
From 18 SMU Boards
Trigger Out to Central Trigger Processor (CTP)
CTP Interface
Ethernet RJ45
FPGA (e. g. Xilinx XC2V2000 FF896)
Detector Control System (DCS) Board
J. Cuveland
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Final GTU Setup
18x 1 SMU 5 TMUs
Trigger Unit
2 Racks (19)
cuveland_at_kip.uni- heidelberg.de
J. Cuveland
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DCS

• Production catastrophy (will know more Fr. Sept
  3rd
• Radiation tests in Oslo indicate same level of
  radiation sensitivity as Altera
• In situ reconfiguration of life chip during
  irradiation successfully demonstrated

21
Radiation Measurements
Start of repair

• shift reg. 32x300

Repair time 4 sec here due to cabling
problems Normal 4 ms
G. Tröger, K. Ullaland
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